Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen
Produktcode
AT91SAM9M10-G45-EK
239
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
Figure 22-16.
Burst Read Access, Latency = 2, SDR-SDRAM Devices
22.5.3
Refresh (Auto-refresh Command)
An auto-refresh command is used to refresh the DDRSDRC. Refresh addresses are generated internally by the
SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these auto-
refresh commands periodically. A timer is loaded with the value in the register DDRSDRC_TR that indicates the
number of clock cycles between refresh cycles. When the DDRSDRC initiates a refresh of an SDRAM device,
internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM device, the slave indi-
cates that the device is busy. A request of refresh does not interrupt a burst transfer in progress.
SDRAM device and incremented after each auto-refresh automatically. The DDRSDRC generates these auto-
refresh commands periodically. A timer is loaded with the value in the register DDRSDRC_TR that indicates the
number of clock cycles between refresh cycles. When the DDRSDRC initiates a refresh of an SDRAM device,
internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM device, the slave indi-
cates that the device is busy. A request of refresh does not interrupt a burst transfer in progress.
22.5.4
Power Management
22.5.4.1
Self Refresh Mode
This mode is activated by setting low-power command bits [LPCB] to ‘01’ in the DDRSDRC_LPR Register
Self refresh mode is used to reduce power consumption, i.e., when no access to the SDRAM device is possible. In
this case, power consumption is very low. In self refresh mode, the SDRAM device retains data without external
clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the
SDRAM device become “don’t care” except CKE, which remains low. As soon as the SDRAM device is selected,
the DDRSDRC provides a sequence of commands and exits self refresh mode.
this case, power consumption is very low. In self refresh mode, the SDRAM device retains data without external
clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the
SDRAM device become “don’t care” except CKE, which remains low. As soon as the SDRAM device is selected,
the DDRSDRC provides a sequence of commands and exits self refresh mode.
The DDRSDRC re-enables self refresh mode as soon as the SDRAM device is not selected. It is possible to define
when self refresh mode will be enabled by setting the register LPR (see
when self refresh mode will be enabled by setting the register LPR (see
), timeout command bit:
• 00 = Self refresh mode is enabled as soon as the SDRAM device is not selected
• 01 = Self refresh mode is enabled 64 clock cycles after completion of the last access
• 10 = Self refresh mode is enabled 128 clock cycles after completion of the last access
As soon as the SDRAM device is no longer selected, PRECHARGE ALL BANKS command is generated followed
by a SELF-REFREFSH command. If, between these two commands an SDRAM access is detected, SELF-
REFREFSH command will be replaced by an AUTO-REFRESH command. According to the application, more
AUTO-REFRESH commands will be performed when the self refresh mode is enabled during the application.
by a SELF-REFREFSH command. If, between these two commands an SDRAM access is detected, SELF-
REFREFSH command will be replaced by an AUTO-REFRESH command. According to the application, more
AUTO-REFRESH commands will be performed when the self refresh mode is enabled during the application.
This controller also interfaces low-power SDRAM. These devices add a new feature: A single quarter, one half
quarter or all banks of the SDRAM array can be enabled in self refresh mode. Disabled banks will be not refreshed
in self refresh mode. This feature permits to reduce the self refresh current. The extended mode register controls
this feature, it includes Temperature Compensated Self Refresh (TSCR), Partial Array Self Refresh (PASR)
quarter or all banks of the SDRAM array can be enabled in self refresh mode. Disabled banks will be not refreshed
in self refresh mode. This feature permits to reduce the self refresh current. The extended mode register controls
this feature, it includes Temperature Compensated Self Refresh (TSCR), Partial Array Self Refresh (PASR)
Latency = 2
SDCLK
col a
A[12:0]
NOP
READ
NOP
BST
NOP
COMMAND
0
BA[1:0]
DaDb
DcDd
DeDf
Dg Dh
D[31:0]
F
DM[3:0]
DQS[1:0]