Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen
Produktcode
AT91SAM9M10-G45-EK
261
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
22.8.7
DDRSDRC Low-power Register
Name:
DDRSDRC_LPR
Address:
0xFFFFE61C (0), 0xFFFFE41C (1)
Access:
Read-write
Reset:
See
• LPCB: Low-power Command Bit
Reset value is “00”.
00 = Low-power Feature is inhibited: no power-down, self refresh and Deep power mode are issued to the SDRAM device.
01 = The DDRSDRC issues a Self Refresh Command to the SDRAM device, the clock(s) is/are de-activated and the CKE
signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
signal is set low. The SDRAM device leaves the self refresh mode when accessed and enters it after the access.
10 = The DDRSDRC issues a Power-down Command to the SDRAM device after each access, the CKE signal is set low.
The SDRAM device leaves the power-down mode when accessed and enters it after the access.
The SDRAM device leaves the power-down mode when accessed and enters it after the access.
11 = The DDRSDRC issues a Deep Power-down Command to the Low-power SDRAM device.
This mode is unique to
Low-power SDRAM devices.
• CLK_FR: Clock Frozen Command Bit
Reset value is “0”.
This field sets the clock low during power-down mode or during deep power-down mode. Some SDRAM devices do not
support freezing the clock during power-down mode or during deep power-down mode. Refer to the SDRAM device data-
sheet for details on this.
support freezing the clock during power-down mode or during deep power-down mode. Refer to the SDRAM device data-
sheet for details on this.
1 = Clock(s) is/are frozen.
0 = Clock(s) is/are not frozen.
• PASR: Partial Array Self Refresh
Reset value is “0”.
This field is unique to Low-power SDRAM.
It is used to specify whether only one quarter, one half or all banks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode.
The values of this field are dependant on Low-power SDRAM devices.
After the initialization sequence, as soon as PASR field is modified, Extended Mode Register in the external device mem-
ory is accessed automatically and PASR bits are updated. In function of the UPD_MR bit, update is done before entering in
self refresh mode or during a refresh command and a pending read or write access.
ory is accessed automatically and PASR bits are updated. In function of the UPD_MR bit, update is done before entering in
self refresh mode or during a refresh command and a pending read or write access.
• TCR: Temperature Compensated Self Refresh
Reset value is “0”.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
UPD_MR
–
–
–
APDE
15
14
13
12
11
10
9
8
–
–
TIMEOUT
DS
TCR
7
6
5
4
3
2
1
0
–
PASR
CLK_FR
LPCB