Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

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SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the cur-
rent peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the
SPI_TDR register as the following format.

+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip

select to assert as defined in 

on CSAAT bit. CSAAT, LASTXFER and CSNAAT bit are discussed in the Peripheral Deselection in 

. 

Note:

1. Optional.

In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce processor overhead.

The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means,
as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the
peripheral selection requires the Mode Register to be reprogrammed.

The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the
Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the periph-
eral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred
through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of
memory size for the buffers, but it provides a very effective means to exchange data with several peripherals with-
out any intervention of the processor.

Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer's size
it has to point to. The PDC will perform the following transfer size depending on the mode and number of bits per
data.

Fixed Mode:

• 8-bit Data:

Byte transfer, 
PDC Pointer Address = Address + 1 byte,
PDC Counter = Counter - 1

• 8-bit to 16-bit Data:

2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC Pointer Address = Address + 2 bytes,
PDC Counter = Counter - 1

Variable Mode:

In variable Mode, PDC Pointer Address = Address +4 bytes and PDC Counter = Counter - 1 for 8 to 16-bit transfer
size. When using the PDC, the TDRE and RDRF flags are handled by the PDC, thus the user’s application does
not have to check those bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF),
TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral DMA Controller and user inter-
face, refer to the PDC section of the product datasheet.