Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen
Produktcode
AT91SAM9M10-G45-EK
393
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
28.6
I/O Line Description
28.7
Product Dependencies
28.7.1
I/O Lines
The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on
the features of the PIO controller used in the product, the pins must be programmed in accordance with their
assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the
input path.
the features of the PIO controller used in the product, the pins must be programmed in accordance with their
assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the
input path.
28.7.2
Power Management
The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the
Advanced Interrupt Controller behavior.
Advanced Interrupt Controller behavior.
The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor
while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without
asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without
asserting the interrupt line of the processor, thus providing synchronization of the processor on an event.
28.7.3
Interrupt Sources
The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0
cannot be used.
cannot be used.
The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system
peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the
interrupt. This is performed by reading successively the status registers of the above mentioned system
peripherals.
peripheral interrupt lines. When a system interrupt occurs, the service routine must first distinguish the cause of the
interrupt. This is performed by reading successively the status registers of the above mentioned system
peripherals.
The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to
external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller.
external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller.
The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO
Controller interrupt lines are connected to the Interrupt Sources 2 to 31.
Controller interrupt lines are connected to the Interrupt Sources 2 to 31.
The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the
bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional opera-
tions and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional opera-
tions and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31.
Table 28-1.
I/O Line Description
Pin Name
Pin Description
Type
FIQ
Fast Interrupt
Input
IRQ0 - IRQn
Interrupt 0 - Interrupt n
Input
Table 28-2.
I/O Lines
Instance
Signal
I/O Line
Peripheral
AIC
FIQ
PD19
B
AIC
IRQ
PD18
B