Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

Produktcode

AT91SAM9M10-G45-EK

419

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

Figure 29-5.

Character Reception

29.5.2.3

Receiver Ready

When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in
DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register
DBGU_RHR is read.

Figure 29-6.

Receiver Ready

29.5.2.4

Receiver Overrun

If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the
RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared
when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.

Figure 29-7.

Receiver Overrun

29.5.2.5

Parity Error

Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with
the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit
PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register
DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status
command is written, the PARE bit remains at 1.

Figure 29-8.

Parity Error

DRXD

True Start Detection

Sampling

Parity Bit

Stop Bit

Example: 8-bit, parity enabled 1 stop

1 bit

period

0.5 bit
period

DRXD

Read DBGU_RHR

RXRDY

DRXD

RSTSTA

RXRDY

OVRE

stop

DRXD

RSTSTA

RXRDY

PARE

Wrong Parity Bit