Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

 46

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The TCMs can be located anywhere in the memory map, with a single region available for ITCM and a separate
region available for DTCM. The TCMs are physically addressed and can be placed anywhere in physical address
space. However, the base address of a TCM must be aligned to its size, and the DTCM and ITCM regions must not
overlap. TCM mapping is performed by using TCM region register (register 9) in CP15. The user should input the
right mapping address for TCMs.

The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU imple-
ments a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple
AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives
the benefit of increased overall bus bandwidth, and a more flexible system architecture.

The multi-master bus architecture has a number of benefits:

• It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture.

• Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is 

required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they 
have to support retry and split transactions.

• The arbitration becomes effective when more than one master wants to access the same slave simultaneously.

The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight
words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that
the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests.

Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for.

All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the
ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time.

The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary bound-
ary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries.

Supported Transfers

SINGLE

Single transfer

Single transfer of word, half word, or byte:

• data write (NCNB, NCB, WT, or WB that has missed in DCache)

• data read (NCNB or NCB)

• NC instruction fetch (prefetched and non-prefetched)

• page table walk read

INCR4

Four-word incrementing burst

Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, 
NCB, WT, or WB write.

INCR8

Eight-word incrementing burst

Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write.

WRAP8

Eight-word wrapping burst

Cache linefill