Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen
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Produktcode
AT91SAM9M10-G45-EK
614
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
33.9.2
SSC Clock Mode Register
Name:
SSC_CMR
Addresses:
0xFFF9C004 (0), 0xFFFA0004 (1)
Access:
Read-write
• DIV: Clock Divider
0 = The Clock Divider is not active.
Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The
minimum bit rate is MCK/2 x 4095 = MCK/8190.
minimum bit rate is MCK/2 x 4095 = MCK/8190.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
DIV
7
6
5
4
3
2
1
0
DIV