Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen
Produktcode
AT91SAM9M10-G45-EK
80
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
12.5.3
Reset Controller Mode Register
Name:
RSTC_MR
Address:
0xFFFFFD08
Access:
Read-write
• URSTEN: User Reset Enable
0 = The detection of a low level on the pin NRST does not generate a User Reset.
1 = The detection of a low level on the pin NRST triggers a User Reset.
• URSTIEN: User Reset Interrupt Enable
0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq.
1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.
• ERSTL: External Reset Length
This field defines the external reset length. The external reset is asserted during a time of 2
(ERSTL+1)
Slow Clock cycles. This
allows assertion duration to be programmed between 60 μs and 2 seconds.
• KEY: Password
Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
31
30
29
28
27
26
25
24
KEY
23
22
21
20
19
18
17
16
–
–
–
–
–
–
–
15
14
13
12
11
10
9
8
–
–
–
–
ERSTL
7
6
5
4
3
2
1
0
–
–
URSTIEN
–
–
–
URSTEN