Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Datenbogen

 929

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to
a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair.
In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data trans-
fer. This is also known as a dual-access transfer.

The DMAC is programmed via the APB interface.

• Two Masters 

• Embeds 8 channels 

• 64 bytes/FIFO for Channel Buffering

• Linked List support with Status Write Back operation at End of Transfer

• Word, HalfWord, Byte transfer support.

• memory to memory transfer

• Peripheral to memory

• Memory to peripheral

The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are also given below in 

• Acting as two Matrix Masters

• Embeds 8 unidirectional channels with programmable priority

• Address Generation

– Source/Destination address programming

– Address increment, decrement or no change

DMA Channel Definition

MCI0

TX/RX

0

SPI0 TX 

1

SPI0

RX

2

SPI1

TX

3

SPI1

RX

4

SSC0

TX

5

SSC0 RX

6

SSC1

TX

7

SSC1

RX

8

AC97C

TX

9

AC97C

RX

10

MCI1

TX/RX

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