Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Datenbogen
Produktcode
AT32UC3A3-XPLD
352
32072H–AVR32–10/2012
AT32UC3A3
19.12.3
Linked List Pointer Register for Channel x
Name: LLPx
Access Type: Read/Write
Offset:
0x010 + [x * 0x58]
Reset Value:
0x00000000
• LOC: Address of the next LLI
Starting address in memory of next LLI if block chaining is enabled.
The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if
block chaining is enabled.
block chaining is enabled.
The LLP register has two functions:
The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer (single or multi-block).
If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to
enabling the channel in order to set up the transfer type.
enabling the channel in order to set up the transfer type.
It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists. In this case,
LOC[29:0] corresponds to A[31:2] of the next Linked Listed Item address
LOC[29:0] corresponds to A[31:2] of the next Linked Listed Item address
The LLPx register is also used to point to the address where write back of the control and source/destination status infor-
mation occurs after block completion.
mation occurs after block completion.
• LMS: List Master Select
Identifies the High speed bus interface for the device that stores the next linked list item:
31
30
29
28
27
26
25
24
LOC[29:22]
23
22
21
20
19
18
17
16
LOC[21:14]
15
14
13
12
11
10
9
8
LOC[13:6]
7
6
5
4
3
2
1
0
LOC[5:0]
LMS
Table 19-3.
List Master Select
LMS
HSB Master
0
HSB master 1
1
HSB master 2
Other
Reserved