Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Datenbogen

32072H–AVR32–10/2012

The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.

The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.

The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the
common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main
clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from
any tapping of this prescaler, or the undivided main clock, as long as f

CPU

 

≥

 

f

PBA,B,

. The synchro-

nous clock source can be changed on-the fly, responding to varying load in the application. The
clock domains can be shut down in sleep mode, as described in 

. Additionally, the

clocks for each module in the four domains can be individually masked, to avoid power con-
sumption in inactive modules.

Synchronous Clock Generation

The common main clock can be connected to the slow clock, Oscillator 0, or PLL0. By default,
the main clock will be connected to the slow clock. The user can connect the main clock to Oscil-
lator 0 or PLL0 by writing the MCSEL field in the Main Clock Control Register (MCCTRL). This
must only be done after that unit has been enabled, otherwise a deadlock will occur. Care
should also be taken that the new frequency of the synchronous clocks does not exceed the
maximum frequency for each clock domain.

Mask

Prescaler

Osc0 clock
PLL0 clock

MCSEL

0

1

CPUSEL

CPUDIV

Main clock

Sleep 

Controller

CPUMASK

CPU clocks

HSB clocks

PBAclocks

PBB clocks

Sleep

instruction

Slow clock