Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Datenbogen
Produktcode
AT32UC3A3-XPLD
553
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-5. Asynchronous Mode Character Reception
25.6.2.4
Synchronous Receiver
In synchronous mode (MR.SYNC is one), the receiver samples the RXD signal on each rising
edge of the Baud Rate Clock, as illustrated in
edge of the Baud Rate Clock, as illustrated in
. If a low level is detected, it is consid-
ered as a start bit. Configuration bits and fields are the same as in asynchronous mode.
Figure 25-6. Synchronous Mode Character Reception
Figure 25-7. Receiver Status
25.6.2.5
Receiver Operations
When a character reception is completed, it is transferred to the Received Character field in the
Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status
Register (CSR.RXRDY) is set. An interrupt request is generated if the Receiver Ready bit in the
Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status
Register (CSR.RXRDY) is set. An interrupt request is generated if the Receiver Ready bit in the
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Parity
Bit
Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
16
samples
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Sampling
Parity Bit
Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
D0
D1
D2
D3
D4
D5
D6
D7
RXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
CR
RXRDY
OVRE
D0
D1
D2
D3
D4
D5
D6
D7
Start
Bit
Parity
Bit
Stop
Bit
RSTSTA = 1
Read
RHR