Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD Datenbogen

32072H–AVR32–10/2012

sources can be cleared by setting corresponding bit in ISCR but DRQ which is cleared once
FIFO has been read/written.

Figure 32-5. Communication example

Host controller supports parallel mode and must be set to parallel interface mode after the Mem-
ory Stick.

– Identify the Memory Stick media and confirm it is a Memory Stick PRO. For Memory 

stick media identification, see “Memory Stick Standard Format Specifications ver. 
1.X Appendix D” or “Memory Stick Standard Format Specifications ver. 2.0 
Application Notes 1.3 Media Identification Process”.

– Set the Memory Stick to parallel interface mode by executing TPC commands 

SET_R/W_REG_ADRS then WRITE_REG to set System Parameter bit PAM=1.

– Write SRAC=0 and REI=0 to the system register (SYS) to switch host controller to 

parallel interface mode.

– Change serial clock (SCLK) while communication is not being performed with the 

Memory Stick.

FIFO direction setting

Write to FIFO

TPC setting

Interrupt wait

MSSYS register

MSDAT register

MSCMD register

Protocol start

FDIR=1

CMD

TPC = SET_CMD

CPU

MSI

Communication
with Memory Stick

Protocol end

MSISCR register

Interrupt enable

MSIER register

PEND=1, MSINT=1

MSISR.PEND=1

Interrupt clear

PEND=1

Interrupt wait

Interrupt clear

MS INT wait

INT from
Memory Stick

INT received

MSISR.MSINT=1

MSISCR register

MSINT=1