Atmel Xplained Pro Evaluation Kit for the ATSAMD21J18A Microcontroller ATSAMD21-XPRO ATSAMD21-XPRO Datenbogen
Produktcode
ATSAMD21-XPRO
439
Atmel | SMART SAM D21 [DATASHEET]
Atmel-42181C–SAM-D21_Datasheet–07/2014
z
Since the transmit buffer no longer contains data, the Transmit Complete interrupt flag (INTFLAG.TXC) is set.
After a collision, software must manually enable the transmitter before continuing. Software must ensure CTRLB
Synchronization Busy bit (SYNCBUSY.CTRLB) is not asserted before re-enabling the transmitter.
Synchronization Busy bit (SYNCBUSY.CTRLB) is not asserted before re-enabling the transmitter.
25.6.3.6 Loop-back Mode
By configuring the Receive Data Pinout (CTRLA.RXPO) and Transmit Data Pinout (CTRLA.TXPO) to use the same data
pins for transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available
externally.
pins for transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available
externally.
25.6.3.7 Start-of-Frame Detection
The USART start-of-frame detector can wake up the CPU when it detects a start bit. In standby sleep mode, the internal
fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source.
fast startup oscillator must be selected as the GCLK_SERCOMx_CORE source.
When a 1-to-0 transition is detected on RxD, the 8MHz Internal Oscillator is powered up and the USART clock is
enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation
to the fast startup internal oscillator start-up time. Refer to
enabled. After startup, the rest of the data frame can be received, provided that the baud rate is slow enough in relation
to the fast startup internal oscillator start-up time. Refer to
for details. The start-
up time of this oscillator varies with supply voltage and temperature.
The USART start-of-frame detection works both in asynchronous and synchronous modes. It is enabled by writing a one
to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable
bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately
when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force
the 8MHz Internal Oscillator and USART clock active while the frame is being received, but the CPU will not wakeup until
the Receive Complete interrupt is generated, if enabled.
to the Start of Frame Detection Enable bit in the Control B register (CTRLB.SFDE). If the Receive Start Interrupt Enable
bit in the Interrupt Enable Set register (INTENSET.RXS) is set, the Receive Start interrupt is generated immediately
when a start is detected. When using start-of-frame detection without the Receive Start interrupt, start detection will force
the 8MHz Internal Oscillator and USART clock active while the frame is being received, but the CPU will not wakeup until
the Receive Complete interrupt is generated, if enabled.
25.6.3.8 Sample Adjustment
In asynchronous mode (CTRLA.CMODE=0), three samples in the middle are used to determine the value based on
majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A
register (CTRLA.SAMPA). When CTRLA.SAMPA is set to zero, samples 7-8-9 are used for 16x over sampling and
samples 3-4-5 are used for 8x over sampling.
majority voting. The three samples used for voting can be selected using the Sample Adjustment bit field in Control A
register (CTRLA.SAMPA). When CTRLA.SAMPA is set to zero, samples 7-8-9 are used for 16x over sampling and
samples 3-4-5 are used for 8x over sampling.
25.6.4 DMA, Interrupts and Events
25.6.4.1 DMA Operation
The USART generates the following DMA requests.
Table 25-3. Module Request for SERCOM USART
Condition
Interrupt
request
Event output
Event input
DMA request
DMA request is
cleared
Data Register Empty
x
x
When data is
written
Transmit Complete
x
Receive Complete
x
x
When data is
read
Receive Start
x
Clear to Send Input
Change
Change
x
Receive Break
x
Error
x