Mikroelektronika MIKROE-738 Datenbogen

mikroC PRO for PIC32

MikroElektronika

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The PIC32MX generates interrupt requests in response to interrupt events from peripheral modules. The Interrupt 

module exists external to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. 

The PIC32MX Interrupts module includes the following features: 

 

- Up to 96 interrupt sources. 

 

- Up to 64 interrupt vectors. 

 

- Single and Multi-Vector mode operations. 

 

- Five external interrupts with edge polarity control. 

 

- Interrupt proximity timer. 

 

- Module freeze in Debug mode. 

 

- Seven user-selectable priority levels for each vector. 

 

- Four user-selectable subpriority levels within each priority. 

 

- User-configurable shadow set based on priority level (this feature is not available on all devices; refer to  

 

  the specific device data sheet for availability). 

 

- Software can generate any interrupt. 

 

- User-configurable interrupt vector table location. 

ISRs are organized in IVT. ISR is defined as a standard function but with the 

iv

 directive afterwards which connects the 

function with specific interrupt vector. For more information on IVT refer to the PIC32 Family Reference Manual.

Configuring Interrupts

The PIC32MX interrupt controller can be configured to operate in one of two modes:

 

- 

Single Vector mode - all interrupt requests will be serviced at one vector address (mode out of reset). 

 

- 

Multi-Vector mode - interrupt requests will be serviced at the calculated vector address. 

 

Single Vector Mode

 

In this mode, the CPU always vectors to the same address. This means that only one ISR can be defined. 

 

The Single Vector mode address is calculated by using the Exception Base (EBase) address (its address  

 

default is 0x9FC01000E). The exact formula for Single Vector mode is as follows: 

 

Multi Vector Mode

 

In this mode, the CPU vectors to the unique address for each vector number. Each vector is located at a  

 

specific offset, with respect to a base address specified by the EBase register in the CPU. 

 

The individual vector address offset is determined by the following equation: 

 

By default, the compiler configures interrupts in the 

Multi Vector mode, with the EBase address set to  

 

0x9FC01000 and vector spacing of 32. 

 

Configuring the Interrupt operating mode is performed in the Edit Project window.