Mikroelektronika MIKROE-738 Datenbogen

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mikoC PRO for PIC32

MikroElektronika

As it can be seem, the entire 4 GB virtual address space is divided into two primary regions: 

User and Kernel space. 

The lower 2 GB of space called 

USEG/KUSEG, and the upper 2 GB are divided into KSEG0, KSEG1, KSEG2 and 

KSEG3.

Virtual vs Physical Addresses

The PIC32MX’s CPU uses virtual addresses to address the peripherals, which means that to access the PIC32MX’s 

peripherals we (and the CPU) must be operating within the virtual boundaries of KSEG1. 

The PIC32MX’s CPU also uses virtual addressing to fetch and execute program memory instructions.

If you look closely, you’ll  see that the physical  address region  between  the 

INTERNAL RAM (at physical address 

0x00000000) and the 

INTERNAL BOOT FLASH (beginning at physical address 0x1FC00000) 

is matched up with the virtual memory schemes of KSEG0 and KSEG1. 

The PIC32MX CPU maps the virtual areas of KSEG0 and KSEG1 against the same physical memory area beginning 

at physical address 0x00000000. 

Because both the KSEG0 and KSEG1 virtual segments point to the same physical memory area, the PIC32MX CPU 

can  execute  instructions  from  either  the  KSEG0  or  KSEG1  virtual  memory  segment,  depending  on  the  cacheable 

status of the application (KSEG0 and USEG-KSEG are cacheable while KSEG1 is not cacheable).

Related topics: Accessing individual bits, SFRs, Memory type specifiers