Mikroelektronika MikroE Development Kits MIKROE-996 Datenbogen
Produktcode
MIKROE-996
PIC18F87K22 FAMILY
DS39960D-page 524
2011 Microchip Technology Inc.
FIGURE 31-24:
A/D CONVERSION TIMING
TABLE 31-28: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
130
T
AD
A/D Clock Period
0.8
12.5
(
µs
T
OSC
-based, V
REF
3.0V
1.4
25
(
µs
V
DD
= 3.0V; T
OSC
-based,
V
REF
full range
—
1
µs
A/D RC mode
—
3
µs
V
DD
= 3.0V; A/D RC mode
131
T
CNV
Conversion Time
(not including acquisition time)
(not including acquisition time)
14
15
T
AD
132
T
ACQ
Acquisition Time
(
1.4
—
µs
-40°C to +125°C
135
T
SWC
Switching Time from Convert
Sample
—
(Note
137
T
DIS
Discharge Time
0.2
—
µs
-40°C to +125°C
Note 1:
The time of the A/D clock period is dependent on the device frequency and the T
AD
clock divider.
2:
ADRES registers may be read on the following T
CY
cycle.
3:
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (V
after the conversion (V
DD
to V
SS
or V
SS
to V
DD
). The source impedance (R
S
) on the input channels is 50
.
4:
On the following cycle of the device clock.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(Note 2)
11
10
9
2
1
0
Note
1:
If the A/D clock source is selected as RC, a time of T
CY
is added before the A/D clock starts. This allows the SLEEP instruction to
be executed.
2:
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
.
. .
. . .
T
CY
(Note 1)