Nxp Semiconductors OM11043 Datenbogen

LPC1769_68_67_66_65_64_63

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© NXP Semiconductors N.V. 2014. All rights reserved.

Two CAN controllers and buses.

Data rates to 1 Mbit/s on each bus.

32-bit register and RAM access.

Compatible with CAN specification 2.0B, ISO 11898-1.

Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) 
receive identifiers for all CAN buses.

Acceptance Filter can provide FullCAN-style automatic reception for selected 
Standard Identifiers.

FullCAN messages can generate interrupts.

The LPC17xx contain a single 12-bit successive approximation ADC with eight channels 
and DMA support.

12-bit successive approximation ADC.

Input multiplexing among 8 pins.

Power-down mode.

Measurement range VREFN to VREFP.

12-bit conversion rate: 200 kHz.

Individual channels can be selected for conversion.

Burst conversion mode for single or multiple inputs.

Optional conversion on transition of input pin or Timer Match signal.

Individual result registers for each ADC channel to reduce interrupt overhead.

DMA support.

The DAC allows to generate a variable analog output. The maximum output value of the 
DAC is VREFP.

Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See 

10-bit DAC

Resistor string architecture

Buffered output

Power-down mode

Selectable output drive

Dedicated conversion timer

DMA support