Intel 1.00 GHz BX80530F1000256 Datenbogen
Produktcode
BX80530F1000256
Datasheet
37
Intel
®
Celeron
®
Processor up to 1.10 GHz
NOTES:
1. Unless otherwise noted, all specifications in this table apply to Celeron
processors at all frequencies.
2. All AC timings for the AGTL+ signals are referenced to the BCLK rising edge at 1.25 V at the processor pin.
All AGTL+ signal timings (address bus, data bus, etc.) are referenced at 1.00 V at the processor pins.
3. Not 100% tested. Specified by design characterization as a clock driver requirement.
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
4. The internal core clock frequency is derived from the processor system bus clock. The system bus clock to
core clock ratio is determined during initialization. Individual processors will only operate at their specified
system bus frequency, either 66 MHz or 100 MHz, not both.
system bus frequency, either 66 MHz or 100 MHz, not both.
processor.
5. The BCLK period allows a +0.5 ns tolerance for clock driver variation. See the appropriate clock synthesizer/
driver specification for details.
6. Due to the difficulty of accurately measuring clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
measured on the rising edges of adjacent BCLKs crossing 1.25 V at the processor pin. The jitter present
must be accounted for as a component of BCLK timing skew between devices.
7. The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the
jitter created by the clock driver. The –20 dB attenuation point, as measured into a 10 to 20 pF load, should
be less than
be less than
500 kHz. This specification may be ensured by design characterization and/or measured with a
spectrum analyzer. See the appropriate clock synthesizer/driver specification for details
8. BCLK Rise time is measure between 0.5 V–2.0 V. BCLK fall time is measured between 2.0 V–0.5 V.
9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of
9. BCLK high time is measured as the period of time above 2.0 V. BCLK low time is measured as the period of
time below 0.5 V.
10.This specification applies to Pentium III
processors operating at a system bus frequency of 66 MHz.
11. This specification applies to Pentium III
processors operating at a system bus frequency of 100 MHz
Table 11. System Bus AC Specifications (SET Clock)
1, 2
T# Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
66.67
100.00
MHz
4
T1: BCLK Period
10.0
10.0
ns
4, 5, 10
4, 5, 11
T2: BCLK Period Stability
±250
±250
ps
6, 7, 10
6, 7, 11
T3: BCLK High Time
2.5
2.5
ns
9, 10
9, 11
T4: BCLK Low Time
2.4
2.4
ns
9, 10
9, 11
T5: BCLK Rise Time
0.4
1.6
ns
3, 8
T6: BCLK Fall Time
0.4
1.6
ns
3, 8