Intel i5-2450M AV8062700995805 Datenbogen
Produktcode
AV8062700995805
•
The processor supports streaming any 3 independent and simultaneous display
combination of DisplayPort*/HDMI*/eDP*/ monitors. In the case of 3
simultaneous displays, two High Definition Audio streams over the digital display
interfaces are supported.
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Each digital port is capable of driving resolutions up to 3840x2160 at 60 Hz using
4 lanes at link data rate HBR2 through DisplayPort* and 4096x2304 at 24 Hz
using HDMI*. Use of active level shifter is required to obtain maximum HDMI
resolution.
•
DisplayPort* Aux CH, DDC channel, Panel power sequencing, and HPD are
supported through the PCH.
Figure 3.
Processor Display Architecture
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Display
Pipe A
Display
Pipe B
Display
Pipe C
P
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F
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HD Audio
Controller
Controller
Transcoder A
DP / HDMI
Timing, VDIP
Transcoder B
DP / HDMI
Timing, VDIP
Transcoder C
DP / HDMI
Timing, VDIP
eDP* Mux
Transcoder eDP*
DP encoder
Timing, VDIP
DPT, SRID
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M
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Audio
Codec
DP
Aux
eDP
X4 eDP
P
C
H
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p
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C
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tr
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S
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D
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B
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C
X4 DP /
HDMI
X4 DP /
HDMI
Display is the presentation stage of graphics. This involves:
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Pulling rendered data from memory
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Converting raw data into pixels
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Blending surfaces into a frame
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Organizing pixels into frames
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Optionally scaling the image to the desired size
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Re-timing data for the intended target
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Formatting data according to the port output standard
DisplayPort*
DisplayPort* is a digital communication interface that uses differential signaling to
achieve a high-bandwidth bus interface designed to support connections between PCs
and monitors, projectors, and TV displays.
Processor—Interfaces
5th Generation Intel
®
Core
™
Processor Family, Intel
®
Core
™
M Processor Family, Mobile Intel
®
Pentium
®
Processor Family, and
Mobile Intel
®
Celeron
®
Processor Family
Datasheet – Volume 1 of 2
March 2015
26
Order No.: 330834-004v1