Intel 9560 CM8063101049716 Datenbogen

41

2. These voltages are target only. A variable voltage source should exist on systems in the event that a different voltage is required. 

See Ararat Voltage Regulator Module Design Guide for more information. 

3. Uncore, Core, and Cache voltage and Current Rating are at the Package Pad.

4. The voltage specification requirements are measured across the VCCCORESENSE and VSSCORESENSE pins using an oscilloscope 

set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 MOhm minimum impedance at the processor 

socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is 

not coupled into the scope probe.

5. The voltage specification requirements are measured across the VCCCACHESENSE and VSSCACHESENSE pins using an 

oscilloscope set to a 100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 mOhms minimum impedance 

at the processor socket. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from 

the system is not coupled into the scope probe.

6. Warm boot reset, only in downward direction.

7. Min and Max range is spec at the die for both VCCIO. This range includes 50 mV p-p AC noise. It also includes any DC and AC 

tolerances at package pin.

8. The FMB remote sense tolerance is ±2.5% for DC to 20 MHz at the package, where ±1.5% is allotted for a DC to 1 MHz range 

and an additional ±1% for 1 MHz to 20 MHz. Similarly, ±6.4% is allotted for DC to 20 MHz at the die. It is expected that VCCIO 

regulators meet ±1.5% at the remote sense location based on the general remote sense termination point location as described 

, VR Sense Point (Representation). For future processor compatibility, it is strongly recommended that the platform 

query the PIROM to assure VCCIO is set to the appropriate level prior to powering up the VCCIO supply.

9. All voltage regulation measurements taken at remote sense termination points.

10.For peak-to-peak Ripple and Noise (R&N) measured with full bandwidth (BW) of the scope (Min 1 GHz BW scope is required):

set scope diff probe and the scope at full BW (capture waveform A, channel 1).

11.For peak-to-peak Ripple and Noise (R&N) measured above 1 MHz: 

 Step 1 = set both: scope diff probe and/or the scope at 1 MHz BW limit (capture waveform B, channel 2).

 Step 2 = calculate A-B (use scope Math function: subtract channel 1 - channel 2).

I

CC_CORE

I

CC 

for core

151

A

I

CC_CORE_TDC

Thermal Design Current for Core

100

A

1

1. ICC_CORE_TDC is the sustained (DC equivalent) current that the processor core is capable of drawing indefinitely and should be 

used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for monitoring its 

temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform the processor 

and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. Please see 

the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing ICC_CORE_TDC 

indefinitely. Refer to 

 for further details on the average processor current draw over various time durations. This 

parameter is based on design characterization and is not tested.

I

CC_CORE_STEP

Max Load step for core

95

A

2

2. During system power on, the pulse inrush (ICC_CORE_STEP) can be as high as 130A peak-to-peak.

d

ICC_CORE/dt

Slew rate for core at Ararat output

154

A/us

I

CC_UNCORE

ICC for uncore

50

A

I

CC_UNCORE_TDC

Thermal Design Current for Uncore

43

A

3

3. ICC_UNCORE_TDC is the sustained (DC equivalent) current that the processor uncore is capable of drawing indefinitely and 

should be used for the Ararat voltage regulator temperature assessment. The Ararat voltage regulator is responsible for 

monitoring its temperature and asserting the VR_FAN_N, VR_THERMALERT_N, VR_THERMTRIP_N signals sequentially to inform 

the processor and platform of a thermal excursion. Of the three signals, only VR_THERMALTERT_N is monitored by the processor. 

Please see the Ararat Voltage Regulator Module Design Guide for further details. The processor is capable of drawing 

ICC_UNCORE_TDC indefinitely. This parameter is based on design characterization and is not tested.

I

CC_UNCORE_STEP

Max Load step for uncore

22

A

4

4. During system power on, the pulse inrush (ICC_UNCORE_STEP) can be as high as 40A peak-to-peak.

dI

CC_UNCORE/dt

Slew rate for uncore at Ararat output

75

A/us

I

CC_IO

ICC for processor I/O

22

A

5

5. The ICC_IO current specification applies to the total current from VCCIO pins.

I

CC_Analog

ICC for processor Analog

4

A

I

CC33_SM

ICC33 for main supply

200

mA