Intel C2550 FH8065401488912 Datenbogen
Produktcode
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
485
Volume 2—Serial Peripheral Interface (SPI)—C2000 Product Family
Soft Flash Protection
22.8
Soft Flash Protection
Two types of Flash protection are not defined in the Flash Descriptor that are supported
by the SPI controller:
1. Flash Range Read and Write Protection
2. Global Write Protection
2. Global Write Protection
22.8.1
Flash Range Read and Write Protection
The SPI controller provides a method for blocking reads and writes to specific ranges in
the Flash when the protected ranges are enabled. This is achieved by checking the read
or write cycle type and the address of the requested command against the base and
limit fields of a read or write protected range. The protected range registers are only
applied to the programmed register accesses and have no effect on direct reads.
Note:
Once the BIOS has locked down the Protected BIOS Range registers, this mechanism
remains in place until the next system reset.
22.8.2
Global Write Protection
The SPI controller has a Write Protection Disable (BCR.WPD) configuration bit. When
BCR.WPD=0b, the BIOS is not able to perform any Write or Erase commands to the
Flash. When BCR.WPD=1b, protection against the BIOS erase and rewrite is disabled.
When the Lock Enable (BCR.LE) bit is set, the BIOS disables this protection only during
the System Management Mode (SMM) execution.
If BCR.LE=1b, the SPI controller confirms that only SMM code succeeds to set
BCR.WPD=1b. In addition, if SCS.SMIWPEN=1b, the SPI controller initiates an SMI
when non-SMM code sets BCR.WPD=1b.
22.9
SPI Flash Device Recommended Pinout
This information is in the Intel
®
Atom™ Processor C2000 Product Family Platform
Design Guide (PDG).