Intel E3845 FH8065301487715 Datenbogen
Produktcode
FH8065301487715
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
1953
17.6
SATA Legacy IO Registers
17.6.1
Primary Command (PCMD)—Offset 0h
Access Method
Default: 00h
Table 192.
Summary of SATA Legacy I/O Registers—LBAR
Offset
Size
Register ID—Description
Default
Value
0h
1
00h
2h
1
00h
4h
4
00000000h
8h
1
00h
Ah
1
00h
Ch
4
00000000h
10h
4
00000000h
14h
4
00000000h
Type:
I/O Register
(Size: 8 bits)
PCMD:
LBAR Type:
PCI Configuration Register (Size: 32 bits)
LBAR Reference:
[B:0, D:19, F:0] + 20h
7
4
0
0
0
0
0
0
0
0
0
RSV
D
0
RWC
RSV
D
1
ST
A
R
T
Bit
Range
Default &
Access
Description
7:4
0b
RO
RSVD0:
Reserved
3
0h
RW
Read / Write Control (RWC):
Sets the direction of the bus master transfer: 0 =
memory to device, 1 = device to memory. This bit must not be changed when the bus
master function is active.
2:1
0b
RO
RSVD1:
Reserved
0
0h
RW
Start/Stop Bus Master (START):
Setting this bit enables bus master operation of the
controller. Bus master operation does not actually start unless the Bus Master Enable bit
in PCI configuration space is also set. Clearing it halts bus master operation. All state
information is lost when this bit is written to 0; Master mode operation cannot be
stopped and then resumed. If this bit is reset while bus master operation is still active
and the device has not yet finished its data transfer, the bus master command is said to
be aborted. If this bit is cleared to 0 prior to the DMA data transfer being initiated by the
drive in a device to memory data transfer, then not DMAT will be sent to terminate the
data transfer. SW intervention (e.g. sending SRST) is required to reset the interface in
this condition. This bit is intended to be cleared by software after the data transfer is
completed - as indicated by either the ACT bit being cleared in the status register, or the
I bit being set in the status register, or both.