Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Electrical Specifications
Intel
®
Atom™ Processor E3800 Product Family
152
Datasheet
NOTES:
1.
The CMD time is measured w.r.t. differential crossing of DRAM_CKP and DRAM_CKN. The tCMDVB and tCMDVA will be
adjusted for proper CMD Setup and Hold time requirement at DRAM. The command timing assumes CMD-1N Mode.
2.
The CTL time is measured w.r.t. differential crossing of DRAM_CKP and DRAM_CKN. The tCTLVB and tCTLVA will be
adjusted for proper CTL Setup and Hold time requirement at DRAM.
3.
The accurate strobe placement using write training algorithm will be performed which will guarantee the required Data
setup/hold time w.r.t. strobe differential crossing at the DRAM input.
4.
The Read training algorithm will center the DQS internally inside DRAM interface in order to have equal tSU and tHD
timings.
5.
All the timing windows are measured at 50% of the respective DRAM signal swing.
T
DVB
+T
VDA
Data, DQ and DM timing window
available at the interface output for
write commands. tDVB is data
available before strobe and tDVA is
data available after corresponding
slope.
available at the interface output for
write commands. tDVB is data
available before strobe and tDVA is
data available after corresponding
slope.
495
ps
3
T
SU
+ T
HD
Data, DQ Input Setup Plus Hold Time
requirement for successful Read
operation. These Setup and Hold
numbers are measured w.r.t.
corresponding strobe or Falling Edge
requirement for successful Read
operation. These Setup and Hold
numbers are measured w.r.t.
corresponding strobe or Falling Edge
255
ps
4
T
DQSS
-120
120
ps
T
WPRE
DQSP/N Preamble duration (one
dummy cycle)
dummy cycle)
0.9
tCKAV
G
T
WPST
DQSP/N Postamble Duration
0.4
tCKAV
G
Figure 21. DDR3L DQ Setup/Hold Relationship to/from DQSP/DQSN (Read Operation)
Table 110. DDR3L Interface Timing Specification (Sheet 3 of 3)
Symbol
Parameter
Min
Max
Unit
Figure
Notes
DQS
Valid Data
DQ
tHD
0. 5 x
DRAM_VDD_S4
tSU
tHD
tSU
DQSN
Valid Data
Valid Data
Valid Data