Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2335
18.7.193 Debug Capability Event Ring Segment Table Base Address
Register (DCERSTBA)—Offset 8490h
The Debug Capability Event Ring Segment Table Base Address Register identifies the
start address of the Debug Capability Event Ring Segment Table.
Access Method
Default: 0000000000000000h
18.7.194 Debug Capability Event Ring Dequeue Pointer Register
(DCERDP)—Offset 8498h
The Debug Capability Event Ring Dequeue Pointer Register is written by software to
define the Debug Capability Event Ring Dequeue Pointer location to the xHC. Software
updates this pointer when it has finished the evaluation of an Event(s) on the Debug
Capability Event Ring.
Access Method
Default: 0000000000000000h
Type:
Memory Mapped I/O Register
(Size: 64 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ER
ST
BA
R
RS
VD
Bit
Range
Default &
Access
Field Name (ID): Description
63:4
000000000
000000h
RW
Event Ring Segment Table Base Address Register (ERSTBAR):
This field defines
the high order bits of the start address of the Debug Capability Event Ring Segment
Table.
Software shall initialize this register before setting the Debug Capability Enable field in
the DCCTRL register to 1.
Power Well:
Core
3:0
0h
RW
Reserved (RSVD):
Reserved.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 64 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
6
3
6
0
5
6
5
2
4
8
4
4
4
0
3
6
3
2
2
8
2
4
2
0
1
6
1
2
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DQ
P
R
SVD
DESI