Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
2474
Datasheet
9
0h
RW
CRS:
Controller Restore State: This command is similar to the USBCMD. CRS bit in host
mode and initiates the restore process. When software sets this bit to '1', the controller
immediately sets DSTS.RSS to '1'. When the controller has finished the restore process,
it sets DSTS.RSS to '0'.
8
0h
RW
CSS:
Controller Save State: This command is similar to the USBCMD. CSS bit in host
mode and initiates the save process. When software sets this bit to '1', the controller
immediately sets DSTS.SSS to '1'. When the controller has finished the save process, it
sets DSTS.SSS to '0'.
7
0h
RW
LHCRST:
Light Host Controller Reset (LHCRST) RO or RW. Optional normative. Default
= 0. If the Light HC Reset Capability (LHRC) bit in the HCCPARAMS register is 1, then
this flag allows the driver to reset the xHC without affecting the state of the ports. A
system software read of this bit as 0 indicates the Light Host Controller Reset has
completed and it is safe for software to re-initialize the xHC. A software read of this bit
as a 1 indicates the Light Host Controller Reset has not yet completed. If not
implemented, a read of this flag shall always return a 0. All registers in the Aux Power
well shall maintain the values that had been asserted prior to the Light Host Controller
Reset. Refer to section 4.23.1 for more information. When this register is exposed by a
Virtual Function (VF), this bit only generates a Light Reset to the xHC instance
presented by the selected VF, e.g. Disable the VFs device slots and set the associated VF
Run bit to Stopped. Refer to section 8 for more information.
6:4
0h
RO
RSVD7:
Reserved
3
0h
RW
HSEE:
Host System Error Enable (HSEE) RW. Default = 0. When this bit is a 1, and the
HSE bit in the USBSTS register is a 1, the xHC shall assert out-of-band error signaling to
the host. The signaling is acknowledged by software clearing the HSE bit. Refer to
section 4.10.2.6 for more information. When this register is exposed by a Virtual
Function (VF), the effect of the assertion of this bit on the Physical Function (PF0) is
determined by the VMM. Refer to section 8 for more information.
2
0h
RW
INTE:
Interrupter Enable (INTE) RW. Default = 0. This bit provides system software
with a means of enabling or disabling the host system interrupts generated by
Interrupters. When this bit is a 1, then Interrupter host system interrupt generation is
allowed, e.g. the xHC shall issue an interrupt at the next interrupt threshold if the host
system interrupt mechanism (e.g. MSI, MSI-X, etc.) is enabled. The interrupt is
acknowledged by a host system interrupt specific mechanism. When this register is
exposed by a Virtual Function (VF), this bit only enables the set of Interrupters assigned
to the selected VF. Refer to section 7.7.2 for more information.
1
0h
RW
HCRST:
Host Controller Reset (HCRST) RW. Default = 0. This control bit is used by
software to reset the host controller. The effects of this bit on the xHC and the Root Hub
registers are similar to a Chip Hardware Reset. When software writes a 1 to this bit, the
Host Controller resets its internal pipelines, timers, counters, state machines, etc. to
their initial value. Any transaction currently in progress on the USB is immediately
terminated. A USB reset shall not be driven on USB2 downstream ports, however a Hot
or Warm Reset shall be initiated on USB3 Root Hub downstream ports. PCI Configuration
registers are not affected by this reset. All operational registers, including port registers
and port state machines are set to their initial values. Software shall reinitialize the host
controller as described in Section 4.1 in order to return the host controller to an
operational state. This bit is cleared to 0 by the Host Controller when the reset process
is complete. Software cannot terminate the reset process early by writing a 0 to this bit
and shall not write any xHC Operational or Runtime registers until while HCRST is 1.
Note, the completion of the xHC reset process is not gated by the Root Hub port reset
process. Software shall not set this bit to 1 when the HCHalted (HCH) bit in the USBSTS
register is a 0. Attempting to reset an actively running host controller may result in
undefined behavior. When this register is exposed by a Virtual Function (VF), this bit
only resets the xHC instance presented by the selected VF. Refer to section 8 for more
information.
Bit
Range
Default &
Access
Description