Intel E3815 FH8065301567411 Datenbogen

 

Intel

®

 Atom™ Processor E3800 Product Family

Datasheet

2873

The Enhanced SSP Time Slot Status registers are read only registers that indicate 

which Time Slot the Enhanced SSP is currently in when the Enhanced SSP is in Network 

Mode (SSCR0.MOD = 1). This register is not valid when the Enhanced SSP is not in 

Network Mode. Note that Writes to reserved bits must be zeroes, and Read value of 

these bits are undetermined.

Default: 00000000h

The Enhanced SSP Audio Clock Divider registers are read-write registers that indicate 

which clock frequency is sent to the Enhanced SSP and to the SYSCLK pin. If 

SSCR0.SCR is not 0, then there is no guaranteed phase relationship between SYSCLK 

and SSPSCLK. The SSPSFRM Frame Synch Sampling Frequency is calculated by dividing 

the chosen PLL output clock frequency (SSACD.ACPS) by the chosen divider 

(SSACD.ACDS) which gives the SYSCLK frequency. The SYSCLK is then divided by 4 (or 

by 1) to get the SSPSCLK. The SSPSCLK is divided by the data size (EDSS, DSS values) 

and by the number of time slots being used (SSCR0.FRDC value), if any, to give the 

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RSVD

RT

S

A

31:8

000000h

RO

Reserved

7:0

00h

RW

0 = SSP will not receive data in this time slot 1 = SSP 

will receive data in this time slot

Memory Mapped I/O Register

(Size: 32 bits)

PCI Configuration Register (Size: 32 bits)

[B:0, D:21, F:0] + 10h

31

28

24

20

16

12

8

4

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

NMBSY

R

SVD

TS

S

31

0b

RO

0 = No frame is currently active (in network mode 

only) 1 = SSP is in network mode and a frame is currently active

30:3

0000000h

RO

Reserved

2:0

000b

RO

Value indicates which time slot is currently active