Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4033
26.14.12 PME Control and Status Register (PMECTRLSTATUS)—Offset 84h
Access Method
Default: 00000008h
18:16
3h
RO
Version (VERSION):
Indicates support for Revision 1.2 of the PCI Power Management
Specification.
15:8
00h
RO
Next Capability (NXTCAP):
Points to the next capability structure. This points to
NULL.
7:0
01h
RO
Power Management Capability (POWER_CAP):
Indicates this is power
management capability.
Bit
Range
Default &
Access
Field Name (ID): Description
Type:
PCI Configuration Register
(Size: 32 bits)
Offset:
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
Re
se
rv
ed
0
PME
S
TA
TUS
Re
se
rv
ed
1
PM
EE
NA
BL
E
Re
se
rv
ed
2
NO_
S
OF
T
_
RESET
Re
se
rv
ed
3
PO
WERS
TA
TE
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Reserved0:
Reserved.
15
0h
RW/1C
PME Status (PMESTATUS):
•
•
0 = Software clears the bit by writing a 1 to it.
•
1 = This bit is set when the AHB Device would normally assert the PME# signal
independent of the state of the PME Enable bit (bit 8 in this register).
14:9
00h
RO
Reserved1:
Reserved.
8
0h
RW
PME Enable (PMEENABLE):
A 1 enables the function to assert PME#. When 0, PME#
message on SB is disabled.
7:4
0h
RO
Reserved2:
Reserved.
3
1h
RO
No_Soft_Reset (NO_SOFT_RESET):
This bit indicates that devices transitioning from
D3hot to D0 because of PowerState commands do not perform an internal reset.
Configuration Context is preserved.
2
0h
RO
Reserved3:
Reserved.