Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
4428
Datasheet
32.6.8
Scratchpad Register (COM1_SCR)—Offset 3FFh
Access Method
Default: 00h
1
0b
RO
Delta Data Set Ready (DDSR):
This is used to indicate that the modem control line
dsr_n has changed since the last time the MSR was read. '0' - no change on dsr_n since
last read of MSR '1' - change on dsr_n since last read of MSR Reading the MSR clears
the DDSR bit. In Loopback Mode (MCR[4] = 1), DDSR reflects changes on MCR[0]
(DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset
occurs (software or otherwise), then the DDSR bit is set when the reset is removed if
the dsr_n signal remains asserted. Note that PCU-UART does not implement the Data
Set Ready (dsr_n) input.
0
0b
RO
Delta Clear to Send (DCTS):
This is used to indicate that the modem control line
cts_n has changed since the last time the MSR was read. '0' - no change on cts_n since
last read of MSR '1' - change on cts_n since last read of MSR Reading the MSR clears the
DCTS bit. In Loopback Mode (MCR[4] = 1), DCTS reflects changes on MCR[1] (RTS).
Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs
(software or otherwise), then the DCTS bit is set when the reset is removed if the cts_n
signal remains asserted. Note that PCU-UART does not implement the Clear to Send
(cts_n) input.
Bit
Range
Default &
Access
Description
Type:
I/O Register
(Size: 8 bits)
COM1_SCR:
7
4
0
0
0
0
0
0
0
0
0
SC
Bit
Range
Default &
Access
Description
7:0
00h
RW
Scratchpad (SC):
This register is for programmers to use as a temporary storage
space.