Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
4513
34.3.52
LPCC—Offset 84h
LPC Control register
Access Method
Default: 00000001h
Bit
Range
Default &
Access
Description
31:7
0b
RO
RSVD0:
Reserved
6
0b
RW
NMI2SMIEN:
NMI to SMI Enable (NMI2SMIEN): When set, instead of NMI messgae SMI
message will be sent.
5
0b
RO
NMI2SMIST:
NMI to SMI bit Status (NMI2SMIST)
4
0b
RW/1C
NMIN:
NMI NOW (NMIN): When set, NMI messgae will be sent. Writing 1'b1 to
NMI_NOW inverts NMI_MOW and NMI_NOW_STS value
3
0b
RO
NMINS:
NMI_NOW_STS is a result of the NMI_NOW configuration bit. Writing 1'b1 to
NMI_NOW inverts NMI_NOW_STS value. Resulting that the first time NMI_NOW is
written sets the NMI_NOW_STS and initiates NMI. Next writing clears the
NMI_NOW_STS and allows initiating NMI by the next writing to NMI_NOW
2
1b
RW
GNMIED:
GPIO NMI Edge Detction (GNMIED): When set, NMI messgae will be sent on
NMI GPIO posedge. when cleared the NMI message will be sent on negedge
1
0b
RW
GNMIE:
GPIO NMI Enable (GNMIE): When set, NMI messgae will be sent when NMI
GPIO occured. when cleared the message will not be sent
0
0b
RW/1C
GNMS (GNMIS):
GPIO NMI Status (GNMIS), when NMI is recieved from GPIO this bit is
set. write '1' to this register to clear the status bit
Type:
Memory Mapped I/O Register
(Size: 32 bits)
LPCC:
ILB_BASE_ADDRESS Type:
PCI Configuration Register (Size: 32
bits)
ILB_BASE_ADDRESS Reference:
ILB_BASE_ADDRESS Reference:
[B:0, D:31, F:0] + 50h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
RSVD0
LP
CCLK
_
S
LC
RSVD1
LPCC
LK
_forc
e_off
CLKRU
N
_EN
LP
CCLK
1
EN
LP
CCLK
0
EN
Bit
Range
Default &
Access
Description
31:9
0b
RO
RSVD0:
Reserved
8
0b
RO
LPCCLK_SLC:
iLPCCLK mux select (0 - ilpcclk0, 1 ilpcclk1)This bit get value from soft
strap.
7:4
0b
RO
RSVD1:
Reserved