Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
923
14.11.250 DSPBADDR—Offset 7117Ch
Display B Async flip Start Address Register
Access Method
Default: 00000000h
Bit
Range
Default &
Access
Field Name (ID): Description
31
0b
RW
HARDWARE_DRIVE_MSA_MISC1_ENABLE:
This bit enables hardware to drive MSA
MISC1 bit3:1 with the stero 3D left/right eye field indication. Hardware will drive 000
when S3D mode is disabled, 001 when enabled and the upcoming video frame is right
eye, 011 when enabled and the upcoming video frame is left eye.
When this bit is disabled, software may manually program the MSA MISC1 Field S3D
field in bit 2:0 in this register to set MISC1 bit 3:1
0 = Disable hardware driving MSA MISC1 bit 3:1. Allow software to manually program
MSA MISC1 bit3:1 through MSA_MISC1_FIELD_S3D (default)
1 = Enable hardware to drive MSA MISC1 bit3:1 for S3D
30:3
0b
RW
RESERVED:
Reserved.
2:0
0b
RW
MSA_MISC1_FIELD_S3D:
This field provides software to manually program MSC1
stero video attribute for DisplayPort:
000 = No stereo video transported
001 = For progressive video, the next (upcoming) video frame is RIGHT eye
010 = Reserved
011 = For progressive video, the next (upcoming) video frame is LEFT eye
100 = Stacked top and bottom top half represents left-eye view and bottom half
represents right-eye view
101 = Stacked top and bottom top half represents right-eye view and bottom half
represents left-eye view
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DIS
P
LA
Y
_
B_ST
AR
T_AD
DRES
S_BIT
S
RE
SERV
ED_MBZ
FLIP_SO
U
RCE
DE
CR
Y
PTION_REQ
UE
ST
RE
SE
RVED
_
M
BZ
_
1