Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
928
Datasheet
14.11.253 DSPBSTRIDE—Offset 71188h
Display B/Sprite Stride Register
Access Method
Default: 00000000h
14.11.254 DSPBKEYVAL—Offset 71194h
Sprite Color Key Value Register
Bit
Range
Default &
Access
Field Name (ID): Description
31:0
0b
RW
DISPLAY_B_OFFSET:
This register provides the panning offset into the display B
plane. This value is added to the surface address to get the graphics address of the first
pixel to be displayed. This offset must be at least pixel aligned. This offset is the
difference between the address of the upper left pixel to be displayed and the display
surface address. When performing 180 rotation, this offset must be the difference
between the last pixel of the last line of the display data in its unrotated orientation and
the display surface address.
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
GTTMMADR_LSB Type:
PCI Configuration Register (Size: 32
bits)
GTTMMADR_LSB Reference:
GTTMMADR_LSB Reference:
[B:0, D:2, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DISPLA
Y
_
B
_
S
PRITE_ST
R
IDE
RE
SERV
ED
Bit
Range
Default &
Access
Field Name (ID): Description
31:6
0b
RW
DISPLAY_B_SPRITE_STRIDE:
This is the stride for display B/Sprite in bytes. When
using linear memory, this must be 64 byte aligned. When using tiled memory, this must
be 512 byte aligned. The maximum value for this register is fixed. This register is
updated through a command packet passed through the command stream or writes to
this register. When it is desired to update both this and the start register, the stride
register must be written first because the write to the start register is the trigger that
causes the update of both registers on the next VBLANK event. When using tiled
memory, the actual memory buffer stride is limited to a maximum of 16K bytes.
[DevBW, DevCL, DevCDV] The display stride must be power of 2 when doing Asynch
Flips.
[DevBW, DevCL, DevCDV] The display stride must be 8KB or greater when doing Asynch
Flips together with 180 rotation.
The value in this register is updated through the command streamer during a
synchronous flip.
5:0
0b
RW
RESERVED:
Reserved.