Intel E3815 FH8065301567411 Datenbogen
Produktcode
FH8065301567411
Intel
®
Atom™ Processor E3800 Product Family
Datasheet
2223
Default: 00000FA0h
18.7.56
Event Ring Segment Table Size 3 (ERSTSZ3)—Offset 2068h
The Event Ring Segment Table Size Register defines the number of segments
supported by the Event Ring Segment Table. There are 8 ERSTSZ registers. x = 1, 2, ...
8.
Access Method
Default: 00000000h
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0
IMODC
IMODI
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RW
Interrupt Moderation Counter (IMODC):
Down counter. Loaded with the IMODI
value whenever IP is cleared to '0', counts down to '0' and stops. The associated
interrupt shall be signaled whenever this counter is '0', the Event Ring is not empty, the
IE and IP flags = '1', and EHB = '0'.
This counter may be written directly by software at any time to alter the interrupt rate.
Power Well:
Core
15:0
0FA0h
RW
Interrupt Moderation Interval (IMODI):
Default = '4000' (~1 ms). Minimum inter-
interrupt interval. The interval is specified in 250ns increments. A value of '0' disables
interrupt throttling logic, and interrupts shall be generated immediately if IP = '0', EHB
= '0', and the Event Ring is not empty.
Power Well:
Core
Type:
Memory Mapped I/O Register
(Size: 32 bits)
Offset:
MBAR Type:
PCI Configuration Register (Size: 64 bits)
MBAR Reference:
[B:0, D:20, F:0] + 10h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rsvd
1
ERST
S
Bit
Range
Default &
Access
Field Name (ID): Description
31:16
0000h
RO
Rsvd1:
Reserved.
Power Well:
Core