Motorola Espresso Maker MC68340 Benutzerhandbuch

MOTOROLA

MC68340 USER’S MANUAL

3- 41

Figure 3-22 is a flowchart showing bus arbitration for a single device. This technique
allows processing of bus requests during data transfer cycles. Refer to Figures 3-23 and
3-24 for bus arbitration timing diagrams.

is negated at the time that

BGACK

is asserted. This type of operation applies to a

system consisting of the MC68340 and one device capable of bus mastership. In a system
having a number of devices capable of bus mastership,

from each device can be wire-

ORed to the MC68340. In such a system, more than one bus request could be asserted
simultaneously.

is negated a few clock cycles after the transition of

BGACK

. However,

if bus requests are still pending after the negation of

, the MC68340 asserts another

within a few clock cycles after it was negated. This additional assertion of

allows

external arbitration circuitry to select the next bus master before the current bus master
has finished using the bus. The following paragraphs provide additional information about
the three steps in the arbitration process. Bus arbitration requests are recognized during
normal processing,

HALT

assertion, and a CPU32 halt caused by a double bus fault.

GRANT BUS ARBITRATION

1. ASSERT BG

TERMINATE ARBITRATION

1. NEGATE BG (AND WAIT FOR

BGACK TO BE NEGATED)

RE-ARBITRATE OR RESUME

PROCESSOR OPERATION

PROCESSOR

REQUESTING DEVICE

REQUEST THE BUS

1. ASSERT BR

ACKNOWLEDGE BUS MASTERSHIP

1. EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2. NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED
3. NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
4. BUS MASTER NEGATES BR

OPERATE AS BUS MASTER

RELEASE BUS MASTERSHIP

1. NEGATE BGACK

1. PERFORM DATA TRANSFERS (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES

Figure 3-22. Bus Arbitration Flowchart for Single Request

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com