ARM Cortex R4F Benutzerhandbuch
Memory Protection Unit
ARM DDI 0363E
Copyright © 2009 ARM Limited. All rights reserved.
7-2
ID013010
Non-Confidential, Unrestricted Access
7.1
About the MPU
The MPU works with the L1 memory system to control accesses to and from L1 and external
memory. For a full architectural description of the MPU, see the ARM Architecture Reference
Manual.
memory. For a full architectural description of the MPU, see the ARM Architecture Reference
Manual.
The MPU enables you to partition memory into regions and set individual protection attributes
for each region. The MPU supports zero, eight, or twelve memory regions.
for each region. The MPU supports zero, eight, or twelve memory regions.
Note
If the MPU has zero regions, you cannot enable or program the MPU. Attributes are only
determined from the default memory map when zero regions are implemented.
determined from the default memory map when zero regions are implemented.
Each region is programmed with a base address and size, and the regions can be overlapped to
enable efficient programming of the memory map. To support overlapping, the regions are
assigned priorities, with region 0 having the lowest priority and region 11 having the highest.
The MPU returns access permissions and attributes for the highest priority region where the
address hits.
enable efficient programming of the memory map. To support overlapping, the regions are
assigned priorities, with region 0 having the lowest priority and region 11 having the highest.
The MPU returns access permissions and attributes for the highest priority region where the
address hits.
The MPU is programmed using CP15 registers c1 and c6, see MPU control and configuration
on page 4-5. Memory region control read and write access is permitted only from Privileged
modes.
on page 4-5. Memory region control read and write access is permitted only from Privileged
modes.
Table 7-1 shows the default memory map.
Table 7-1 Default memory map
Address
range
range
Instruction memory type
Data memory type
Execute Never
Instruction
cache enabled
cache enabled
Instruction
cache disabled
cache disabled
Data cache
enabled
enabled
Data cache
disabled
disabled
0xFFFFFFFF
Normal
Non-cacheable
only if HIVECS is
TRUE
Non-cacheable
only if HIVECS is
TRUE
Normal
Non-cacheable
only if HIVECS is
TRUE
Non-cacheable
only if HIVECS is
TRUE
Strongly Ordered
Strongly
Ordered
Ordered
Instruction
execution only
permitted if
HIVECS is TRUE
execution only
permitted if
HIVECS is TRUE
0xF0000000
0xEFFFFFFF
-
-
Strongly Ordered
Strongly
Ordered
Ordered
Execute Never
0xC0000000
0xBFFFFFFF
-
-
Shared Device
Shared
Device
Device
Execute Never
0xA0000000
0x9FFFFFFF
-
-
Non-shared
Device
Device
Non-shared
Device
Device
Execute Never
0x80000000
0x7FFFFFFF
Normal,
Cacheable,
Non-shared
Cacheable,
Non-shared
Normal,
Non-cacheable,
Non-shared
Non-cacheable,
Non-shared
Normal,
Non-cacheable,
Shared
Non-cacheable,
Shared
Normal,
Non-cacheable,
Shared
Non-cacheable,
Shared
Instruction
execution permitted
execution permitted
0x60000000
0x5FFFFFF
Normal,
Cacheable,
Non-shared
Cacheable,
Non-shared
Normal,
Non-cacheable,
Non-shared
Non-cacheable,
Non-shared
Normal,
WT Cacheable,
Non-shared
WT Cacheable,
Non-shared
Normal,
Non-cacheable,
Shared
Non-cacheable,
Shared
Instruction
execution permitted
execution permitted
0x40000000
0x3FFFFFFF
Normal,
Cacheable,
Non-shared
Cacheable,
Non-shared
Normal,
Non-cacheable,
Non-shared
Non-cacheable,
Non-shared
Normal,
WBWA Cacheable
, Non-shared
WBWA Cacheable
, Non-shared
Normal,
Non-cacheable,
Shared
Non-cacheable,
Shared
Instruction
execution permitted
execution permitted
0x00000000