Epson Multi-mode Data Controller MFJ-1278B Benutzerhandbuch
MFJ-1278B MULTI-MODE HARDWARE
Watch-dog Timer
Inverters U7c, U7d, U7e, and Q10 and Q20 provide a "watch- dog" timer on the transmit key
line to ensure that the transmitter does not remain keyed for more than about 30 seconds
should the TNC fails. This allows you to leave a station (such as a remote digipeater) on-the-
air and unattended without much chance of having a malfunction "lock up" the packet
channel. This also helps ensure compliance with FCC regulations regarding unattended
station operation.
Jumper JMP4 is provided for testing purposes. When JMP4 is installed, timing capacitor
C31 is shunted, disabling the watch-dog timer.
line to ensure that the transmitter does not remain keyed for more than about 30 seconds
should the TNC fails. This allows you to leave a station (such as a remote digipeater) on-the-
air and unattended without much chance of having a malfunction "lock up" the packet
channel. This also helps ensure compliance with FCC regulations regarding unattended
station operation.
Jumper JMP4 is provided for testing purposes. When JMP4 is installed, timing capacitor
C31 is shunted, disabling the watch-dog timer.
Modem
U16, an XR2206, is a Frequency Shift Keying (FSK) modulator that generates an audio data
signal for use by the radio transmitter. Two tones are used, one for each digital level, and
these tones may be calibrated via trimpots R77/R78, R105/R106, R119/R122 and R139/R138
in conjunction with the on-board calibration support circuitry and software. When the
transmitter is not being keyed, transistor Q9 is switched on, thus preventing U16 from
producing tones. This allows you to leave a microphone connected to your packet transmitter
for voice operation.
R157 and R158 are used to set the audio output levels to the transmitter.
U20, an XR2211, provides a Phase Locked Loop (PLL) FSK demodulator. It converts the
received audio FSK signals into digital data at standard logic levels. This data is sent to the
state machine clock recovery and NRZI to NRZ format conversion circuits. Trimpots R79,
R113, R114 and R115 are used to calibrate the PLL demodulator's free-running frequency
that is set midway between the FSK tones being received. These tones are measured by the
calibration software and the output signal produced by U8a and U8b, which is a frequency
doubling shaping circuit.
signal for use by the radio transmitter. Two tones are used, one for each digital level, and
these tones may be calibrated via trimpots R77/R78, R105/R106, R119/R122 and R139/R138
in conjunction with the on-board calibration support circuitry and software. When the
transmitter is not being keyed, transistor Q9 is switched on, thus preventing U16 from
producing tones. This allows you to leave a microphone connected to your packet transmitter
for voice operation.
R157 and R158 are used to set the audio output levels to the transmitter.
U20, an XR2211, provides a Phase Locked Loop (PLL) FSK demodulator. It converts the
received audio FSK signals into digital data at standard logic levels. This data is sent to the
state machine clock recovery and NRZI to NRZ format conversion circuits. Trimpots R79,
R113, R114 and R115 are used to calibrate the PLL demodulator's free-running frequency
that is set midway between the FSK tones being received. These tones are measured by the
calibration software and the output signal produced by U8a and U8b, which is a frequency
doubling shaping circuit.
Power Supply
Regulator Q3 and associated components provide a +5 volt regulated output for the MFJ-
1278B digital logic circuitry. In order to reduce conducted RFI from the digital power
source, series inductor L1 is provided. Transistor Q4, in conjunction with CMOS the
inverters in U14, provide a "power failure" circuit for the battery-backed RAM chips to
ensure that RAM is in the "power-down" state when the main power is removed. In addition,
this circuit provides the main power- on reset signal via U7f.
1278B digital logic circuitry. In order to reduce conducted RFI from the digital power
source, series inductor L1 is provided. Transistor Q4, in conjunction with CMOS the
inverters in U14, provide a "power failure" circuit for the battery-backed RAM chips to
ensure that RAM is in the "power-down" state when the main power is removed. In addition,
this circuit provides the main power- on reset signal via U7f.