Epson Multi-mode Data Controller MFJ-1278B Benutzerhandbuch
MFJ-1278B MULTI-MODE PACKET RADIO PROTOCOL
The communications chip recognizes the opening and closing flags and passes the address,
control, and data fields, including PID to the software. The FCS field is a Frame Check
Sequence computed by the transmitting chip and sent with the frame. The receiving chip
recomputes the FCS based on the data received and rejects any frames in which the received
FCS does not match the computed FCS. There is virtually no chance of an undetected bad
frame using this method. This satisfies the level two task of bad data detection.
The MFJ-1278B uses the Zilog 8440 SIO communication chip. The Zilog 8440 operates in
conjunction with a two-chip "state machine" that is used to recover the data clock. The
transmitted data is encoded in NRZI form, that encodes a "0" data bit as a transition in the
encoded bit stream and a "1" data bit as no transition. The data encoding in conjunction with
the bit stuffing, ensures that no more than five "1"'s occur in a row, except when FLAG bytes
are being transmitted, guarantees that a logic level transition occurs at least once every 5 bit
times. These frequent transitions allow the receiver to synchronize its clock with the
transmitter. Other chips that are compatible with the SIO and the "state machine" are the
Western Digital 1933/1935, the Intel 8273, used on the VADCG and Ashby TNCs and the
Zilog 8530, used on the Xerox 820 FAD adapter.
While the AX.25 protocol uses the HDLC format supplied by the communications chip, there
are several other Layer Two concerns. The other Layer Two concerns being duplicate frame
detection, connection and disconnection of the Level Two layers on a different TNCs, and
buffer overrun avoidance. The AX.25 protocol solves these problems as described below.
control, and data fields, including PID to the software. The FCS field is a Frame Check
Sequence computed by the transmitting chip and sent with the frame. The receiving chip
recomputes the FCS based on the data received and rejects any frames in which the received
FCS does not match the computed FCS. There is virtually no chance of an undetected bad
frame using this method. This satisfies the level two task of bad data detection.
The MFJ-1278B uses the Zilog 8440 SIO communication chip. The Zilog 8440 operates in
conjunction with a two-chip "state machine" that is used to recover the data clock. The
transmitted data is encoded in NRZI form, that encodes a "0" data bit as a transition in the
encoded bit stream and a "1" data bit as no transition. The data encoding in conjunction with
the bit stuffing, ensures that no more than five "1"'s occur in a row, except when FLAG bytes
are being transmitted, guarantees that a logic level transition occurs at least once every 5 bit
times. These frequent transitions allow the receiver to synchronize its clock with the
transmitter. Other chips that are compatible with the SIO and the "state machine" are the
Western Digital 1933/1935, the Intel 8273, used on the VADCG and Ashby TNCs and the
Zilog 8530, used on the Xerox 820 FAD adapter.
While the AX.25 protocol uses the HDLC format supplied by the communications chip, there
are several other Layer Two concerns. The other Layer Two concerns being duplicate frame
detection, connection and disconnection of the Level Two layers on a different TNCs, and
buffer overrun avoidance. The AX.25 protocol solves these problems as described below.
AX.25 LEVEL TWO
The foundation for the AX.25 protocol is the Balanced Link Access Procedure or BLAP of
the CCITT X.25 standard. BLAP in turn conforms to the HDLC standard. The AX.25
protocol adds two extensions to BLAP, extended address fields and unnumbered information,
or UI frames. BLAP limits addresses to eight bits, while AX.25 uses from 112 to 560 bits,
containing the originator's call sign, the destination call sign and an optional list of one to
eight digipeater and simplex digital repeater call signs.
The AX.25 protocol uses the UI frames to send information, bypassing the normal flow
control and acknowledgment protocol. The UI frame is not acknowledged and is transmitted
at layer two without fear of disturbing higher layers. The AX.25 protocol also uses UI frames
for beacons frames, automatic identification packets, and for sending information frames
when the MFJ-1278B is not connected to another TNC, e.g., CQ and QSO activities.
The ARRL publication Amateur Packet-Radio Link-Layer Protocol AX.25 Version 2.0
shows the exact specification for the AX.25 protocol. The TAPR implementation adheres to
this standard for AX.25 version 2.0. The implementation of version 1.0 is almost identical to
the TAPR TNC 1 version of AX.25 protocol in software releases 3.x. This provides
the CCITT X.25 standard. BLAP in turn conforms to the HDLC standard. The AX.25
protocol adds two extensions to BLAP, extended address fields and unnumbered information,
or UI frames. BLAP limits addresses to eight bits, while AX.25 uses from 112 to 560 bits,
containing the originator's call sign, the destination call sign and an optional list of one to
eight digipeater and simplex digital repeater call signs.
The AX.25 protocol uses the UI frames to send information, bypassing the normal flow
control and acknowledgment protocol. The UI frame is not acknowledged and is transmitted
at layer two without fear of disturbing higher layers. The AX.25 protocol also uses UI frames
for beacons frames, automatic identification packets, and for sending information frames
when the MFJ-1278B is not connected to another TNC, e.g., CQ and QSO activities.
The ARRL publication Amateur Packet-Radio Link-Layer Protocol AX.25 Version 2.0
shows the exact specification for the AX.25 protocol. The TAPR implementation adheres to
this standard for AX.25 version 2.0. The implementation of version 1.0 is almost identical to
the TAPR TNC 1 version of AX.25 protocol in software releases 3.x. This provides