Xilinx LogiCore PLB PCI Full Bridge Benutzerhandbuch

DS508 March 21, 2006

www.xilinx.com

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The PLB PCI Full Bridge design provides full bridge 
functionality between the Xilinx 64-bit PLB and a 32-bit 
Revision 2.2 compliant Peripheral Component 
Interconnect (PCI) bus. The bridge is referred to as the 
PLB PCI Bridge in this document.

The Xilinx PLB is a 64-bit bus subset of the IBM PLB 
described in the 64-Bit Processor Local Bus Architecture 
Specification v3.5. Details on the Xilinx PLB and the PLB 
IPIF are found in the Processor IP Reference Guide. This 
guide is accessed via EDK help or the Xilinx website at: 

The LogiCORE PCI v3.0 core provides an interface with 
the PCI bus. Details of the LogiCORE PCI 32 v3.0 core 
operation is found in the 

Xilinx LogiCORE PCI Interface 

 and the 

Host bridge functionality (often called North bridge 
functionality) is an optional functionality. 
Configuration Read and Write PCI commands can be 
performed from the PLB-side of the bridge. The PLB 
PCI Bridge supports a 32-bit/33 MHz PCI bus only.

Exceptions to the support of PCI commands supported 
by the v3.0 core are outlined in the 

The PLB PCI Bridge design has parameters that allow 
customers to configure the bridge to suit their 
application. The parameterizable features of the design 
are discussed in the 

 section.

Core Specifics

Supported Device 
Family

Virtex™-II Pro, Virtex-4

Version of Core

plb_pci

v1.00a

Virtex-IIP

Min

Max

I/O (PCI)

49

50

I/O (PLB-related)

397

433

LUTs

3350

3870

FFs

2570

2970

Block RAMs

8

8

Documentation

Product Specification

Design File Formats

VHDL

Constraints File

example UCF-file

Verification

N/A

Instantiation Template

N/A

Reference Designs

None

Xilinx Implementation 
Tools

8.1.1i or later

Verification

N/A

Simulation

ModelSim SE/EE 5.8d or later

Synthesis

XST

Support provided by Xilinx, Inc.