Philips 8-bit microcontroller with two-clock 80C51 core UM10109 Benutzerhandbuch

 

© Koninklijke Philips Electronics N.V. 2005. All rights reserved.

5

AWP

Activate Write Protection bit. When this bit is cleared, the internal Write Enable flag is forced to the set 
state, thus writes to the flash memory are always enabled. When this bit is set, the Write Enable internal 
flag can be set or cleared using the Set Write Enable (SWE) or Clear Write Enable (CWE) commands.

6

CWP

Configuration Write Protect bit. Protects inadvertent writes to the user programmable configuration 
bytes (UCFG1, BOOTVEC, and BOOTSTAT). If programmed to a logic 1, the writes to these registers 
are disabled. If programmed to a logic 0, writes to these registers are enabled. 

This bit is set by programming the BOOTSTAT register. This bit is cleared by writing the Clear 
Configuration Protection (CCP) command to FMCON followed by writing 96H to FMDATA. 

7

DCCP

Disable Clear Configuration Protection command. If Programmed to ‘1’, the Clear Configuration 
Protection (CCP) command is disabled during ISP or IAP modes. This command can still be used in 
ICP or parallel programmer modes. If programmed to ‘0’, the CCP command can be used in all 
programming modes. This bit is set by programming the BOOTSTAT register. This bit is cleared by 
writing the Clear Configuration Protection (CCP) command in either ICP or parallel programmer modes.