Intel 440GX Benutzerhandbuch
Intel
®
440GX AGPset Design Guide
3-31
Design Checklist
•
Poll the power button status bit during POST while SMIs are not loaded and go directly to soft-
off if it gets set.
off if it gets set.
•
Always install an SMI handler for the power button that operates until ACPI is enabled.
•
Emergency Override: Pressing the power button for 4 seconds goes directly to S5.
•
This is only to be used in EMERGENCIES when software is locked-up.
•
This will cause user data to be lost in most cases.
•
Do not promote pressing the power button for 4 seconds as the normal mechanism to power
the machine off - this violates ACPI.
the machine off - this violates ACPI.
•
To be compliant with the latest PC97 Specification, machines must appear off to the user when
in the S1-S4 sleeping states. This includes:
in the S1-S4 sleeping states. This includes:
•
All lights except a power state light must be off.
•
The system must be inaudible: Silent or stopped fan; drives are off.
•
Note: Contact Microsoft* for the latest information concerning PC97 and Microsoft* Logo
programs.
programs.
3.16
Miscellaneous
•
The 32 kHz oscillator is always required by the PIIX4/PIIX4E, even if the internal RTC is not
used. Also, if the internal RTC in the PIIX4/PIIX4E is not used, an on board battery is not
required at the PIIX4/PIIX4E, but is required for an external implementation of the RTC (e.g.,
RTC in the Super I/O). In this case, connect VCC(RTC) pin of the PIIX4/PIIX4E directly to
3VSB voltage.
used. Also, if the internal RTC in the PIIX4/PIIX4E is not used, an on board battery is not
required at the PIIX4/PIIX4E, but is required for an external implementation of the RTC (e.g.,
RTC in the Super I/O). In this case, connect VCC(RTC) pin of the PIIX4/PIIX4E directly to
3VSB voltage.
•
With the exception of GPI1, all unused GPIx inputs on the PIIX4E should be tied high through
pull-up resistors (8.2K ohm - 10K ohm) to a power plane. Tying directly to the power plane is
also acceptable. GPI1, if not used, should be tied to 3VSB through an 8.2K ohm resistor. If
GPI1 is left floating, this will violate ACPI compliance by preventing the GPI_STS bit
(register base + 0Ch, bit 9) from functioning properly. Note that GPI1 is tied to the resume
well.
pull-up resistors (8.2K ohm - 10K ohm) to a power plane. Tying directly to the power plane is
also acceptable. GPI1, if not used, should be tied to 3VSB through an 8.2K ohm resistor. If
GPI1 is left floating, this will violate ACPI compliance by preventing the GPI_STS bit
(register base + 0Ch, bit 9) from functioning properly. Note that GPI1 is tied to the resume
well.
•
To maintain RTC accuracy, the external capacitor values for the RTC crystal circuit should be
chosen to provide the manufacturer’s specified load capacitance for the crystal when combined
with the parasitic capacitance of the trace, socket (if used), and package, which can vary from
0pF to 8pF. When choosing the capacitors, the following equation can be used:
chosen to provide the manufacturer’s specified load capacitance for the crystal when combined
with the parasitic capacitance of the trace, socket (if used), and package, which can vary from
0pF to 8pF. When choosing the capacitors, the following equation can be used:
Specified Crystal Load = (Cap1 * Cap2)/(Cap1 + Cap2) + parasitic
capacitance
•
The reference board uses 18pF capacitors and an Ecliptek EC38T crystal, which has a
specified load of 12.5pF.
specified load of 12.5pF.
•
When the PIIX4/PIIX4E internal RTC is used, ensure that the VBAT pin of the SMC Ultra IO
device, FDC37932FR, is connected to ground through a pull-down resistor between 1K and 0
ohms. Consult your IO device vendor for implementation guidelines for this or other IO
devices.
device, FDC37932FR, is connected to ground through a pull-down resistor between 1K and 0
ohms. Consult your IO device vendor for implementation guidelines for this or other IO
devices.
•
Recommendations for New Board Designs to minimize ESD events that may cause loss of
CMOS contents:
CMOS contents:
— Provide a 1uF X5R dielectric, monolithic, ceramic capacitor between the VCCRTC pin of
the PIIX4/PIIX4E and the ground plane. This capacitor’s positive connection should not