Ampro Corporation XTX 820 Benutzerhandbuch
Chapter 3
Hardware
XTX 820
Reference Manual
47
J4
Pin #
Pin #
Signal
40-
Pin #
Pin #
Description
GND
22
Ground
54
PIDE_IOW*
23
Drive I/O Write – Strobe signal for write functions. Negative edge
enables data from a register or data port of the drive onto the host
data bus. Positive edge latches data at the host.
enables data from a register or data port of the drive onto the host
data bus. Positive edge latches data at the host.
GND
24
Ground
52
PIDE_IOR*
25
Drive I/O Read – Strobe signal for read functions. Negative edge
enables data from a register or data port of the drive onto the host
data bus. Positive edge latches data at the host.
enables data from a register or data port of the drive onto the host
data bus. Positive edge latches data at the host.
GND
26
Ground
48
PIDE_RDY
27
I/O Channel Ready – When negated extends the host transfer cycle
of any host register access when the drive is not ready to respond to
a data transfer request. High impedance if asserted.
of any host register access when the drive is not ready to respond to
a data transfer request. High impedance if asserted.
90
CBLID_P*
28
Cable ID Select – Used to detects the presence of an 80 conductor
IDE cable on the primary IDE channel. This allows BIOS or
system software to determine if is necessary to enable high-speed
transfer modes (DMA66 or DMA100).
IDE cable on the primary IDE channel. This allows BIOS or
system software to determine if is necessary to enable high-speed
transfer modes (DMA66 or DMA100).
46
PIDE_AK*
29
DMA Channel Acknowledge – Used by the host to acknowledge
data has been accepted or data is available. Used in response to
DMARQ asserted.
data has been accepted or data is available. Used in response to
DMARQ asserted.
GND
30
Ground
44
PIDE_INTRQ
31
Drive Interrupt Request (IRQ 14)– Asserted by drive when it has
pending interrupt (PIO transfer of data to or from the drive to the
host).
pending interrupt (PIO transfer of data to or from the drive to the
host).
NC
NC
32
Not Connected
40
PIDE_A1
33
Drive Address Bus 1 – Used (0 to 2) to indicate which byte in the
ATA command block or control block (register) is being accessed.
ATA command block or control block (register) is being accessed.
NC
PDIAG*
34
Not Connected (Passed Diagnostics)
38
PIDE_A0
35
Drive Address Bus 0 – Used (0 to 2) to indicate which byte in the
ATA command block or control block (register) is being accessed.
ATA command block or control block (register) is being accessed.
36
PIDE_A2
36
Drive Address Bus 2 – Used (0 to 2) to indicate which byte in the
ATA command block or control block (register) is being accessed.
ATA command block or control block (register) is being accessed.
32
PIDE_CS1*
37
Chip Select 1 – Used to select the host-accessible Command Block
Register.
Register.
30
PIDE_CS3*
38
Chip Select 3 – Used to select the host-accessible Command Block
Register.
Register.
NC
DASP*
39
Not Connected (Drive Active/Drive Present)
GND
40
Ground
Notes: The shaded area denotes power or ground. The signals marked with * = Negative true logic.