Digi NS9215 Benutzerhandbuch

Hardware Reference NS9215

The boot-over-SPI operation is performed in two steps. 

In the first step, the hardware fetches the 16-byte header. The data rate for 
this step is about 375 Kbps and completes in less than 0.5ms.

In the second step, the hardware fetches the image at the user-specified data 
rate. Calculate time to completion for this step as shown:

Time(s) = (1 / data_rate) * IMAGE

For example, with a 20 Mbps data rate and a 256 KB (2Mb) image, the time 
to completion is approximately 105ms.

0x14

DynamicRefresh

See the Memory Controller chapter.
For example, the value of this entry is 0x00000025 given 
a 74.9 MHz AHB clock and a 7.8125μs refresh period.

Ox18

DynamicReadConfig

See the Memory Controller chapter.

0x1c

DynamictRP

See the Memory Controller chapter

Ox20

DynamictRAS

See the Memory Controller chapter

Ox24

DynamictSREX

See the Memory Controller chapter

Ox28

DynamictAPR

See the Memory Controller chapter

Ox2c

DynamictDAL

See the Memory Controller chapter

Ox30

DynamictWR

See the Memory Controller chapter

Ox34

DynamictRC

See the Memory Controller chapter

Ox38

DynamictRFC

See the Memory Controller chapter

Ox3c

DynamictXSRt

See the Memory Controller chapter

Ox40

DynamictRRD

See the Memory Controller chapter

Ox44

DynamictMRD

See the Memory Controller chapter

Ox48

DynamictConfig0

See the Memory Controller chapter.
Field B (buffer enable, in the DynamicConfig0 register) 
should be set to 0 (buffers disabled). The buffers will be 
enabled by hardware as part of the boot process.

Ox4c

DynamictRasCas0

See the Memory Controller Chapter

Ox50-
Ox7c

Reserved

Ox80

Boot Code

First 4 bytes of boot code