DCS Computer Hardware dCS 974 Benutzerhandbuch
dCS 974 User Manual
Manual for Software Version 1.0x
dCS Ltd
May 2001
Manual part no: DOC1241121A1
Page 76
Document No: OS-MA-A0124-112.1A1
Contact
dCS
on + 44 1799 531 999
email to: more@dcsltd.co.uk
(inside the UK replace + 44 with 0)
web site: www.dcsltd.co.uk
Clocking
The sample clock quality significantly determines the output performance of a
DDC, in as far as items connected may have to reconstitute an analogue signal,
and may ultimately derive their clock from the DDC clock.
DDC, in as far as items connected may have to reconstitute an analogue signal,
and may ultimately derive their clock from the DDC clock.
The highest quality clocks that are available are crystals, so we use these. In
Internal sync mode, the dCS 974 uses one of two on-board voltage controlled
crystal oscillators (VCXOs) as clock sources – one for 48 kS/s related outputs
and one for 44.1 kS/s related outputs.
Internal sync mode, the dCS 974 uses one of two on-board voltage controlled
crystal oscillators (VCXOs) as clock sources – one for 48 kS/s related outputs
and one for 44.1 kS/s related outputs.
The internal VCXO is synchronised to the sync source (which need not be the
signal input) by a phase locked loop (PLL). The PLL is of a special narrow
bandwidth type, that provides a significant degree of "clock cleaning" - but even
so, signal quality may degrade if particularly poor slave clocks are used. A
consequence of the narrow bandwidth is that it takes quite a long time for the
PLL to lock to a new clock frequency – of the order of 2 seconds. The PLL uses
DSP assistance to keep this time acceptable.
signal input) by a phase locked loop (PLL). The PLL is of a special narrow
bandwidth type, that provides a significant degree of "clock cleaning" - but even
so, signal quality may degrade if particularly poor slave clocks are used. A
consequence of the narrow bandwidth is that it takes quite a long time for the
PLL to lock to a new clock frequency – of the order of 2 seconds. The PLL uses
DSP assistance to keep this time acceptable.
The input data is extracted using an oversampled UART type of decoder. This
can tolerate quite jittery inputs, whose phase is unrelated to the clock source
used for locking. The average frequency must be the same, however.
can tolerate quite jittery inputs, whose phase is unrelated to the clock source
used for locking. The average frequency must be the same, however.
Internal clock
Accuracy when shipped
± 10 ppm
Long Term Stability
± 10 ppm/year at room temperature
Temperature Stability
± 15 ppm over operating temperature range
Synchronising to source
Pull in range
± 300 ppm about nominal frequency
Lock in time
< 2 seconds for most combinations
The PLL is very robust, and will lock to very poor signals if necessary. Data is
decoded using a much wider band (faster) PLL, so AES3 type low frequency
jitter on the input clock can be handled, and will be cleaned.
decoded using a much wider band (faster) PLL, so AES3 type low frequency
jitter on the input clock can be handled, and will be cleaned.
If you need to synchronise several items of digital equipment, we recommend
using a dCS 992 Master Clock.
using a dCS 992 Master Clock.