Barco Projector 26-0313000-00 Benutzerhandbuch
54
Encore Presentation System • User’s Guide • Rev 04
2. Hardware Orientation
Video Processors
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The figure below illustrates a close-up of the M/E connectors on the VPx. Even though the
figure uses M/E 1’s board, all M/E connections are identical on the VPx.
figure uses M/E 1’s board, all M/E connections are identical on the VPx.
Figure 2-6. M/E Connectors, VPx
On each M/E, one input connection is provided for layer A, one for layer B, and two “Link”
connectors for inter-Processor communications.
connectors for inter-Processor communications.
Following are descriptions of each M/E connector on a VPx.
a)
DVI Input A
One DVI-I connector is provided for both digital and analog inputs to the M/E’s
Layer
Layer
A and background channel.
~
Digital
— connect a digital graphics source directly, or connect the
output of a digital graphics router.
~
Analog
— using the appropriate adapter cable, connect an analog VGA
source directly, or connect the output of a VGA router.
Refer to the “
” section on page 56 for important details on the use
of this connector’s analog component. In Appendix A, refer to the “
Note
The M/E connectors on a VPx are identical to those on a VP,
minus the analog and HD/SDI connectors.
minus the analog and HD/SDI connectors.
DVI
INPUT 1A
DVI
INPUT 1B
OUT
IN
SOURCE LINK 1
a
b
c
d
a)
c)
d)
b)
Important
In a widescreen configuration, a VPx cannot function in a
standalone manner, but must always work downstream of a
standard VP. Here, a VPx cannot be the first processor in an
Encore configuration.
standalone manner, but must always work downstream of a
standard VP. Here, a VPx cannot be the first processor in an
Encore configuration.
In the special widescreen “preview” configuration, a VPx can
be used as a standalone destination that accepts DVI input
signals only — but no other input types are accepted, and no
genlock circuitry is provided.
be used as a standalone destination that accepts DVI input
signals only — but no other input types are accepted, and no
genlock circuitry is provided.