Nova Natural NOVA-7820 VIA C3 Processor CPU Embedded Board Benutzerhandbuch

4.6 Advanced Chipset Setup Selections

AMIBIOS SETUP – ADVANCED CHIPSET SETUP

Memory Hole Disabled

SDRAM Timing by SPD Disabled

DRAM Refresh 15.6uS

DRAM Cycle time (SCLKs) 7/9

CAS# Latency (SCLKs) 3

RAS to CAS delay (SCLKs) 3

SDRAM RAS# Precharge (SCLKs) 3

Internal Graphics Mode Size 1MB

Display Cache Window Size 64MB

AGP Aperture Window 64MB

USB Function All USB Port

USB Device Legacy Support Disabled

Port 64/60 Emulation Disabled

Available Options:

> Disabled

Enabled

ESC: Exit ↑↓: Sel
PgUp/PgDn: Modify

F1: Help F2/F3: Color

Figure 4: Advanced Chipset Setup

Memory Hold

This field allows you to reserve an address space for ISA devices that

require it. Configuration options: [Disabled] [15MB-16MB]

SDRAM Timing by SPD

This sets the optimal timings for items "DRAM Refresh", "DRAM Cycle time",

"CAS# Latency", "RAS to CAS delay" and "SDRAM RAS# Precharge",

depending on the memory modules that you are using.

DRAM Cycle time (SCLKs)

This feature controls the number of SDRAM clocks used for SDRAM

parameters Tras and Trc. Tras specifies the minimum clocks required

between active command and precharge command. Trc specifies the

minimum clocks required between active command and re-active command.

CAS# Latency (SCLs)

This controls the latency between the SDRAM read command and the time

that the data actually becomes available.

RAS to CAS Delay (SCLKs)

This controls the latency between the SDRAM active command and the

read/write command.

SDRAM RAS# Precharge (SCLKs)

This controls the idle clocks after issuing a precharge command to the

SDRAM.

Display Cache Window Size

This feature allows you to select the size of mapped memory for Display

Cache data.