Motorola DSP56012 Benutzerhandbuch
4-30
DSP56012 User’s Manual
MOTOROLA
Parallel Host Interface
Host Interface (HI)
4.4.5.5.2
CVR Reserved—Bit 6
This reserved bit is unused and read by the host processor as 0.
4.4.5.5.3
CVR Host Command (HC)—Bit 7
The Host Command (HC) bit is used by the host processor to handshake the
execution of host command interrupts. Normally, the host processor sets HC to
request the host command interrupt from the DSP. When the host command
interrupt is acknowledged by the DSP, the HC bit is cleared by the HI hardware. The
host processor can read the state of HC to determine when the host command has
been accepted. The host processor can elect to clear the HC bit, canceling the host
command interrupt request at any time before it is accepted by the DSP CPU.
execution of host command interrupts. Normally, the host processor sets HC to
request the host command interrupt from the DSP. When the host command
interrupt is acknowledged by the DSP, the HC bit is cleared by the HI hardware. The
host processor can read the state of HC to determine when the host command has
been accepted. The host processor can elect to clear the HC bit, canceling the host
command interrupt request at any time before it is accepted by the DSP CPU.
Note:
Once HC is set, the command interrupt might be recognized by the DSP and
executed before it can be canceled by the host, even if the host clears the HC
bit.
executed before it can be canceled by the host, even if the host clears the HC
bit.
Setting HC causes the Host Command Pending bit (HCP in the HSR) to be set. The
host can write HC and HV in the same write cycle if desired.
host can write HC and HV in the same write cycle if desired.
Note:
Hardware reset, software reset, individual reset, and Stop mode clear HC.
4.4.5.6
Interrupt Status Register (ISR)
The Interrupt Status Register (ISR) is an 8-bit read-only status register used by the
host processor to interrogate the status and flag bits of the HI. The host processor can
write to this address without affecting the internal state of the HI. This is allows a
program to access all of the HI registers by stepping through the HI addresses. The
ISR can not be accessed by the DSP. The status bits are described in the following
paragraphs.
host processor to interrogate the status and flag bits of the HI. The host processor can
write to this address without affecting the internal state of the HI. This is allows a
program to access all of the HI registers by stepping through the HI addresses. The
ISR can not be accessed by the DSP. The status bits are described in the following
paragraphs.
4.4.5.6.1
ISR Receive Data Register Full (RXDF)—Bit 0
The Receive Data register Full (RXDF) bit indicates that the receive byte registers
(RXH, RXM, and RXL) contain data from the DSP CPU and can be read by the host
processor. RXDF is set when the HOTX is transferred to the receive byte registers.
RXDF is cleared when the Receive data Low (RXL) register is read by the host
processor. RXL is normally the last byte of the receive byte registers to be read by the
host processor. RXDF can be cleared by the host processor using the initialize
function. RXDF can be used to assert the external HOREQ pin if the RREQ bit is set.
Regardless of whether the RXDF interrupt is enabled, RXDF provides valid status so
that polling techniques can be used by the host processor.
(RXH, RXM, and RXL) contain data from the DSP CPU and can be read by the host
processor. RXDF is set when the HOTX is transferred to the receive byte registers.
RXDF is cleared when the Receive data Low (RXL) register is read by the host
processor. RXL is normally the last byte of the receive byte registers to be read by the
host processor. RXDF can be cleared by the host processor using the initialize
function. RXDF can be used to assert the external HOREQ pin if the RREQ bit is set.
Regardless of whether the RXDF interrupt is enabled, RXDF provides valid status so
that polling techniques can be used by the host processor.
Note:
Hardware reset, software reset, individual reset, and Stop mode clear RXDF.