Motorola DSP56012 Benutzerhandbuch
4-62
DSP56012 User’s Manual
MOTOROLA
Parallel Host Interface
Host Interface (HI)
When the transfer to HORX occurs within the HI, HRDF is set. Assuming HRIE = 1, a
host receive interrupt will be generated. The interrupt routine must read the HORX
to clear HRDF.
host receive interrupt will be generated. The interrupt routine must read the HORX
to clear HRDF.
Note:
The transfer of data from the TXH, TXM, TXL registers to the HORX register
automatically loads the DMA address counter from the HM1 and HM0 bits in
the DMA (in the host-to-DSP mode). This DMA address is used with the HI to
place the received byte in the correct register (TXH, TXM, or TXL).
automatically loads the DMA address counter from the HM1 and HM0 bits in
the DMA (in the host-to-DSP mode). This DMA address is used with the HI to
place the received byte in the correct register (TXH, TXM, or TXL).
transfers. The interrupt rate is three times faster for 8-bit data transfers than for 24-bit
transfers. TXL is always loaded last.
transfers. TXL is always loaded last.
4.4.8.3.2
Host to DSP—DMA Procedure
The following procedure outlines the typical steps that the host processor must take
to setup and terminate a host-to-DSP DMA transfer (see
to setup and terminate a host-to-DSP DMA transfer (see
1. Set up the external DMA controller (1) source address, byte count, direction,
and other control registers. Enable the DMA controller channel.
2. Initialize the HI (2) by writing the ICR to select the word size (HM0 and HM1),
to select the direction (TREQ = 1, RREQ = 0), and to initialize the channel
setting INIT = 1 (see
setting INIT = 1 (see
3. The DSP’s destination pointer (3) used in the DMA interrupt handler (for
example, an address register) must be initialized and HRIE must be set to
enable the HRDF interrupt to the DSP CPU. This procedure can be done with
a separate host command interrupt routine in the DSP. HOREQ will be
asserted (4) immediately by the HI to begin the DMA transfer.
enable the HRDF interrupt to the DSP CPU. This procedure can be done with
a separate host command interrupt routine in the DSP. HOREQ will be
asserted (4) immediately by the HI to begin the DMA transfer.
4. Perform other tasks (5) while the DMA controller transfers data (6) until
interrupted by the DMA controller DMA transfer complete interrupt (7). The
DSP Interrupt Control Register (ICR), the Interrupt Status Register (ISR), and
RXH, RXM, and RXL registers can be accessed at any time by the host
processor but the TXH, TXM and TXL registers can not be accessed until the
DMA mode is disabled.
DSP Interrupt Control Register (ICR), the Interrupt Status Register (ISR), and
RXH, RXM, and RXL registers can be accessed at any time by the host
processor but the TXH, TXM and TXL registers can not be accessed until the
DMA mode is disabled.
5. Terminate the DMA controller channel (8) to disable DMA transfers.
6. Terminate the DSP-to-DMA mode (9) in the ICR by clearing the HM1 and
HM0 bits and clearing TREQ.