Motorola DSP56012 Benutzerhandbuch
8-8
DSP56012 User’s Manual
MOTOROLA
Digital Audio Transmitter
DAX Internal Architecture
8.5.3
DAX Audio Data Shift Register (XADSR)
The XADSR is a 27-bit shift register that shifts the 24-bit audio data and the 3-bit
non-audio data for one sub-frame. The contents of XADRA are directly transferred to
the XADSR at the beginning of the frame transmission (at the beginning of the
Channel A sub-frame transmission). At the same time, the three bits of non-audio
data(V-bit, U-bit and C-bit) for Channel A in the DAX control register is transferred
to the three highest-order bits of the XADSR. At the beginning of the Channel B
transmission, audio and non-audio data for Channel B is transferred from the
XADBUF and the XNADBUF to the XADSR for shifting. The data in the XADSR is
shifted toward the lowest-order bit at the fifth to thirty-first bit slot of each sub-frame
transmission. This register is not directly accessible by DSP instructions.
non-audio data for one sub-frame. The contents of XADRA are directly transferred to
the XADSR at the beginning of the frame transmission (at the beginning of the
Channel A sub-frame transmission). At the same time, the three bits of non-audio
data(V-bit, U-bit and C-bit) for Channel A in the DAX control register is transferred
to the three highest-order bits of the XADSR. At the beginning of the Channel B
transmission, audio and non-audio data for Channel B is transferred from the
XADBUF and the XNADBUF to the XADSR for shifting. The data in the XADSR is
shifted toward the lowest-order bit at the fifth to thirty-first bit slot of each sub-frame
transmission. This register is not directly accessible by DSP instructions.
8.5.4
DAX Control Register (XCTR)
The XCTR is a 24-bit read/write register that controls the DAX operation. It also
holds the three bits of non-audio data for a frame. The contents of the XCTR are
shown in
holds the three bits of non-audio data for a frame. The contents of the XCTR are
shown in
paragraphs.
8.5.4.1
DAX Enable (XEN)—Bit 0
When the XEN bit is set, the DAX is enabled. If the DAX Stop (XSTP) control bit is set,
XEN is sampled at every frame boundary, thus clearing XEN during the middle of a
frame transmission will stop transmission at the next frame boundary. If XSTP is
cleared, clearing XEN stops the DAX immediately (individual reset).
XEN is sampled at every frame boundary, thus clearing XEN during the middle of a
frame transmission will stop transmission at the next frame boundary. If XSTP is
cleared, clearing XEN stops the DAX immediately (individual reset).
Note:
This bit is cleared by software reset and hardware reset.
8.5.4.2
DAX Interrupt Enable (XIEN)—Bit 1
When the XIEN bit is set, the DAX interrupt is enabled and sends an interrupt
request signal to the DSP if the XADE status bit is set. When this bit is cleared, the
DAX interrupt is disabled.
request signal to the DSP if the XADE status bit is set. When this bit is cleared, the
DAX interrupt is disabled.
Note:
This bit is cleared by software reset and hardware reset.
8.5.4.3
DAX Stop Control (XSTP)—Bit 2
The XSTP bit selects how the DAX is disabled. When this bit is cleared, disabling the
DAX (by clearing XEN) stops the frame transmission immediately. When this bit is
set, disabling the DAX is done at the next frame boundary after finishing the current
frame transmission.
DAX (by clearing XEN) stops the frame transmission immediately. When this bit is
set, disabling the DAX is done at the next frame boundary after finishing the current
frame transmission.
Note:
This bit is cleared by software reset and hardware reset.