Intel 8XC196MC Benutzerhandbuch
5-17
STANDARD AND PTS INTERRUPTS
PI_MASK
Address:
Reset State:
1FBCH
AAH
The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests
associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow
timer interrupt (OVRTM).
associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow
timer interrupt (OVRTM).
7
0
8XC196MC
—
—
—
WG
—
OVRTM2
—
OVRTM1
7
0
8XC196MD
—
COMP5
—
WG
—
OVRTM2
—
OVRTM1
7
0
8XC196MH
—
SP1
—
SP0
—
OVRTM2
—
OVRTM1
Bit
Number
Bit
Mnemonic
Function
7, 5, 3, 1
—
Reserved; for compatibility with future devices, write zeros to these bits.
6
— (MC)
Reserved; for compatibility with future devices, write zero to this bit.
COMP5 (MD)
EPA Compare Channel 5
Setting this bit enables the EPA compare channel 5 interrupt.
The EPA compare channel 5 and the waveform generator interrupts are
associated with the peripheral interrupt (PI). Setting INT_MASK1.5
enables PI.
associated with the peripheral interrupt (PI). Setting INT_MASK1.5
enables PI.
SP1 (MH)
Serial Port 1 Error
Setting this bit enables the serial port 1 error interrupt.
The serial port 1 and serial port 0 error interrupts are associated with the
serial port interrupt (SPI). Setting INT_MASK1.4 enables SPI.
serial port interrupt (SPI). Setting INT_MASK1.4 enables SPI.
4
WG (MC, MD)
Waveform Generator
Setting this bit enables the waveform generator interrupt.
The waveform generator and the EPA compare channel 5 interrupts are
associated with the peripheral interrupt (PI). Setting INT_MASK1.5
enables PI.
associated with the peripheral interrupt (PI). Setting INT_MASK1.5
enables PI.
SP0 (MH)
Serial Port 0 Error
Setting this bit enables the serial port 0 error interrupt.
The serial port 0 and serial port 1 error interrupts are associated with the
serial port interrupt (SPI). Setting INT_MASK1.4 enables SPI.
serial port interrupt (SPI). Setting INT_MASK1.4 enables SPI.
2
OVRTM2
Timer 2 Overflow/Underflow
Setting this bit enables the timer 2 overflow/underflow interrupt.
The timer 2 and timer 1 overflow/underflow interrupts are associated with
the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
enables OVRTM.
the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
enables OVRTM.
Figure 5-9. Peripheral Interrupt Mask (PI_MASK) Register