Intel 8XC196MC Benutzerhandbuch
8XC196MC, MD, MH USER’S MANUAL
5-20
5.5.2
Determining the Source of an Interrupt
When hardware detects an interrupt, it sets the corresponding bit in the INT_PEND or
INT_PEND1 register (Figures 5-10 and 5-11 ). It sets the bit even if the individual interrupt is
disabled (masked). Hardware clears the pending bit when the program vectors to the interrupt ser-
vice routine. The interrupt service routine can read INT_PEND and INT_PEND1 to determine
which interrupts are pending.
INT_PEND1 register (Figures 5-10 and 5-11 ). It sets the bit even if the individual interrupt is
disabled (masked). Hardware clears the pending bit when the program vectors to the interrupt ser-
vice routine. The interrupt service routine can read INT_PEND and INT_PEND1 to determine
which interrupts are pending.
Software can generate an interrupt by setting a bit in INT_PEND or INT_PEND1 register. We
recommend the use of the read-modify-write instructions, such as AND and OR, to modify these
registers.
recommend the use of the read-modify-write instructions, such as AND and OR, to modify these
registers.
ANDB INT_PEND, #11111110B
; Clears the OVRTM pending bit
ORB
INT_PEND, #00000001B
; Sets the OVRTM pending bit
Other methods could result in a partial interrupt cycle. For example, an interrupt could occur dur-
ing an instruction sequence that loads the contents of the interrupt pending register into a tempo-
rary register, modifies the contents of the temporary register, and then writes the contents of the
temporary register back into the interrupt pending register. If the interrupt occurs during one of
the last four states of the second instruction, it will not be acknowledged until after the completion
of the third instruction. Because the third instruction overwrites the contents of the interrupt pend-
ing register, the jump to the interrupt vector will not occur.
ing an instruction sequence that loads the contents of the interrupt pending register into a tempo-
rary register, modifies the contents of the temporary register, and then writes the contents of the
temporary register back into the interrupt pending register. If the interrupt occurs during one of
the last four states of the second instruction, it will not be acknowledged until after the completion
of the third instruction. Because the third instruction overwrites the contents of the interrupt pend-
ing register, the jump to the interrupt vector will not occur.
The PI (MD), SPI (MH), and OVRTM (Mx) interrupts have multiple sources. Read PI_PEND
(Figure 5-12 on page 5-23) to determine which source generated the interrupt request. Reading
PI_PEND clears all the bits. PI_PEND is a read-only register.
(Figure 5-12 on page 5-23) to determine which source generated the interrupt request. Reading
PI_PEND clears all the bits. PI_PEND is a read-only register.